JPS54105424A - Coding circuit - Google Patents

Coding circuit

Info

Publication number
JPS54105424A
JPS54105424A JP1436978A JP1436978A JPS54105424A JP S54105424 A JPS54105424 A JP S54105424A JP 1436978 A JP1436978 A JP 1436978A JP 1436978 A JP1436978 A JP 1436978A JP S54105424 A JPS54105424 A JP S54105424A
Authority
JP
Japan
Prior art keywords
code
run
roms
counter
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1436978A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hayazaki
Noriyoshi Ogata
Masamichi Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1436978A priority Critical patent/JPS54105424A/en
Publication of JPS54105424A publication Critical patent/JPS54105424A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To obtain a circuit which binary-codes a facisimile picture signal, etc., by a relatively-simple method, by dividing the output of a run-length measuring counter into high-order and low-order digits and by reading two fixed memories with both groups taken as addresses.
CONSTITUTION: Gate 1 allows white or black signal period clocks (ϕ1) to pass through, and counter 3 counts this. Then, ROMs 4 and 5 are stored with the MH code of the run-length between 0 and 63 and the number of bits of the code, and ROMs 6 and 7 are with the MH code of the run-length, a multiple of 64, and the number of bits of the code. By the output of counter 3, those ROMs 4 to 7 are read out and their outputs are set to shift registers 8 and 11, and counters 9 and 12. Contents of registers 8 and 11 are read out sequentially as coded outputs from a high-order digit by read clock (ϕ2) controlled by gate circuit groups including counters 9 and 12 and flip-flop 18 and 21.
COPYRIGHT: (C)1979,JPO&Japio
JP1436978A 1978-02-06 1978-02-06 Coding circuit Pending JPS54105424A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1436978A JPS54105424A (en) 1978-02-06 1978-02-06 Coding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1436978A JPS54105424A (en) 1978-02-06 1978-02-06 Coding circuit

Publications (1)

Publication Number Publication Date
JPS54105424A true JPS54105424A (en) 1979-08-18

Family

ID=11859124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1436978A Pending JPS54105424A (en) 1978-02-06 1978-02-06 Coding circuit

Country Status (1)

Country Link
JP (1) JPS54105424A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06158788A (en) * 1992-11-25 1994-06-07 Amex Kiyouhan:Kk Roofing tile panel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06158788A (en) * 1992-11-25 1994-06-07 Amex Kiyouhan:Kk Roofing tile panel

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