JPS5498175A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5498175A
JPS5498175A JP436078A JP436078A JPS5498175A JP S5498175 A JPS5498175 A JP S5498175A JP 436078 A JP436078 A JP 436078A JP 436078 A JP436078 A JP 436078A JP S5498175 A JPS5498175 A JP S5498175A
Authority
JP
Japan
Prior art keywords
lead
pellet
affix
heating
relative positional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP436078A
Other languages
Japanese (ja)
Inventor
Shunji Koike
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP436078A priority Critical patent/JPS5498175A/en
Publication of JPS5498175A publication Critical patent/JPS5498175A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To improve the relative positional accuracy between a pellet and lead by firmly fixing to a ceramic base by a frame used for connection between leads.
CONSTITUTION: Coat low melting point glass 9 on the raised surface of ceramic base 10 and set inner side lead 6 on it. Melt layer 9 by heating it and fix it by cooling. Remove from inner lead 6 the portion 8 used as cavity that has been processed for easy separation. Set pellet 12, affix it and connect the wire. Place cap 13 coated with glass layer 17 and affix it by heating. The dimension remains unchanged since the base lead 6 is fixed without removing the joint which connects lead 6. Therefore, the relative positional accuracy between the pellet and lead is very high and wires can be connected automatically.
COPYRIGHT: (C)1979,JPO&Japio
JP436078A 1978-01-20 1978-01-20 Preparation of semiconductor device Pending JPS5498175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP436078A JPS5498175A (en) 1978-01-20 1978-01-20 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP436078A JPS5498175A (en) 1978-01-20 1978-01-20 Preparation of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP59081778A Division JPS6024046A (en) 1984-04-25 1984-04-25 Lead frame

Publications (1)

Publication Number Publication Date
JPS5498175A true JPS5498175A (en) 1979-08-02

Family

ID=11582203

Family Applications (1)

Application Number Title Priority Date Filing Date
JP436078A Pending JPS5498175A (en) 1978-01-20 1978-01-20 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5498175A (en)

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