JPS5492033A - Controlling method for arithmetic processing unit - Google Patents

Controlling method for arithmetic processing unit

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Publication number
JPS5492033A
JPS5492033A JP15788877A JP15788877A JPS5492033A JP S5492033 A JPS5492033 A JP S5492033A JP 15788877 A JP15788877 A JP 15788877A JP 15788877 A JP15788877 A JP 15788877A JP S5492033 A JPS5492033 A JP S5492033A
Authority
JP
Japan
Prior art keywords
command
memory
control command
counter
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15788877A
Other languages
Japanese (ja)
Inventor
Masao Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15788877A priority Critical patent/JPS5492033A/en
Publication of JPS5492033A publication Critical patent/JPS5492033A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To improve the program processing speed by reading the next command from the memory and shortening the cycle time by the access time of memory while executing a sequence by control command according to the type of execution command of the arithmetic unit.
CONSTITUTION: In case of the control method where the execution command is read out of memory 1 and arithmetic process is executed in operational unit by providing memory 1 where program counter 5 and execution command are stored, the "OR" of control command timing h from sequence logic 6 when the output of decoder 3 is a control command and non-control command timing i when the output of decoder 3 is other than control command is processed by OR gate 7, a signal that advances the contents of counter 5 by one is made and, then, a new execution command is read out in the stage where the execution command is being executed when the control command is neither the memory reference command nor the operation command of counter 5.
COPYRIGHT: (C)1979,JPO&Japio
JP15788877A 1977-12-29 1977-12-29 Controlling method for arithmetic processing unit Pending JPS5492033A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15788877A JPS5492033A (en) 1977-12-29 1977-12-29 Controlling method for arithmetic processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15788877A JPS5492033A (en) 1977-12-29 1977-12-29 Controlling method for arithmetic processing unit

Publications (1)

Publication Number Publication Date
JPS5492033A true JPS5492033A (en) 1979-07-20

Family

ID=15659599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15788877A Pending JPS5492033A (en) 1977-12-29 1977-12-29 Controlling method for arithmetic processing unit

Country Status (1)

Country Link
JP (1) JPS5492033A (en)

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