JPS5491029A - Memory circuit - Google Patents
Memory circuitInfo
- Publication number
- JPS5491029A JPS5491029A JP15786477A JP15786477A JPS5491029A JP S5491029 A JPS5491029 A JP S5491029A JP 15786477 A JP15786477 A JP 15786477A JP 15786477 A JP15786477 A JP 15786477A JP S5491029 A JPS5491029 A JP S5491029A
- Authority
- JP
- Japan
- Prior art keywords
- input
- input part
- input terminal
- trt4
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To realize operation with low power consumption by composing an input part controlling memory cells of two transistors and several diodes, and to attain independent ON-OFF control of cells arrayed in a matrix. CONSTITUTION:The input part of memory cell 2 stored with information is provided with input terminals (x) and (y) and control input part 1 supplied with pieces of information from DATA and ME, and this input part 1 is with two transistors TrT1 and TrT4 and two diodes D1 and D2 or more. The collector of TrT1 of this control part 1 is connected to the input part of memory cell 2, its base is to the emitter or collector of TrT4, and its emitter is to diode D1 with its cathode side connected to input terminal DATA; and the base of TrT4 is connected to input terminal (y) via resistance R1, and its collector or emitter is to input terminal (x). Further, the cathode of diode D2 is connected to input terminal ME and the anode of diode D2 is to the base of TrT1, thereby controlling memory cell 2.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15786477A JPS5491029A (en) | 1977-12-28 | 1977-12-28 | Memory circuit |
US05/971,109 US4288862A (en) | 1977-12-21 | 1978-12-19 | Memory circuit |
CA318,288A CA1114502A (en) | 1977-12-21 | 1978-12-20 | Memory circuit |
DE2855342A DE2855342C2 (en) | 1977-12-21 | 1978-12-21 | Memory circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15786477A JPS5491029A (en) | 1977-12-28 | 1977-12-28 | Memory circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5491029A true JPS5491029A (en) | 1979-07-19 |
JPS5738990B2 JPS5738990B2 (en) | 1982-08-18 |
Family
ID=15659050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15786477A Granted JPS5491029A (en) | 1977-12-21 | 1977-12-28 | Memory circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5491029A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5292443A (en) * | 1976-01-30 | 1977-08-03 | Hitachi Ltd | Memory circuit |
JPS52125244A (en) * | 1976-04-14 | 1977-10-20 | Hitachi Ltd | Memory circuit |
-
1977
- 1977-12-28 JP JP15786477A patent/JPS5491029A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5292443A (en) * | 1976-01-30 | 1977-08-03 | Hitachi Ltd | Memory circuit |
JPS52125244A (en) * | 1976-04-14 | 1977-10-20 | Hitachi Ltd | Memory circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS5738990B2 (en) | 1982-08-18 |
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