JPS5478672A - Complementary silicon gate mos field effect semiconductor device and its manufacture - Google Patents

Complementary silicon gate mos field effect semiconductor device and its manufacture

Info

Publication number
JPS5478672A
JPS5478672A JP14626577A JP14626577A JPS5478672A JP S5478672 A JPS5478672 A JP S5478672A JP 14626577 A JP14626577 A JP 14626577A JP 14626577 A JP14626577 A JP 14626577A JP S5478672 A JPS5478672 A JP S5478672A
Authority
JP
Japan
Prior art keywords
film
region
type
diffusion
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14626577A
Other languages
Japanese (ja)
Inventor
Koji Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14626577A priority Critical patent/JPS5478672A/en
Publication of JPS5478672A publication Critical patent/JPS5478672A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate an easy production of the device as well as to reduce the dispersion for the threshold voltage of P-channel, by providing previously the N- type well region on the P-type semiconductor substrate and then forming N-channel Si gate MOSFET on the well region. CONSTITUTION:N-type well region 2 is formed through diffusion within P-type Si substrate 1, and the entire surface is covered with the lamination film of thin SiO2 film 3 and Si3N4 film 4 to be then removed excluding the areas on the diffusion region and the Si gate MOSFET forming region. Then a heat treatment is given to grow thick field SiO2 film 5 at the exposed region to secure the LOCOS structure, and the window is frilled to the remaining lamination film to form through diffusion P-type region 7 including the source and the drain of the P-channel. And the surface is protected with SiO2 film 6 formed then. After this, the lamination film is removed to coat gate SiO2 film 8 and 8' there, and gate electrode 11 and 11' omposed of poly crystal Si are provided on film 8 and 8'. Then N-type region 9 is formed through diffusion across electrode 11', and at the same time the conductive property is given to both electrode 11 and 11'.
JP14626577A 1977-12-05 1977-12-05 Complementary silicon gate mos field effect semiconductor device and its manufacture Pending JPS5478672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14626577A JPS5478672A (en) 1977-12-05 1977-12-05 Complementary silicon gate mos field effect semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14626577A JPS5478672A (en) 1977-12-05 1977-12-05 Complementary silicon gate mos field effect semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5478672A true JPS5478672A (en) 1979-06-22

Family

ID=15403820

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14626577A Pending JPS5478672A (en) 1977-12-05 1977-12-05 Complementary silicon gate mos field effect semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5478672A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013570A (en) * 1989-05-16 1991-05-07 Yamanashi Yagen Limited Method of producing odorless ripe juice of houttuynia cordata
US6611031B2 (en) 2000-09-28 2003-08-26 Nec Corporation Semiconductor device and method for its manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5013570A (en) * 1989-05-16 1991-05-07 Yamanashi Yagen Limited Method of producing odorless ripe juice of houttuynia cordata
US6611031B2 (en) 2000-09-28 2003-08-26 Nec Corporation Semiconductor device and method for its manufacture

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