JPS5476042A - Multiple processor system - Google Patents

Multiple processor system

Info

Publication number
JPS5476042A
JPS5476042A JP12368378A JP12368378A JPS5476042A JP S5476042 A JPS5476042 A JP S5476042A JP 12368378 A JP12368378 A JP 12368378A JP 12368378 A JP12368378 A JP 12368378A JP S5476042 A JPS5476042 A JP S5476042A
Authority
JP
Japan
Prior art keywords
processor system
multiple processor
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12368378A
Other languages
English (en)
Other versions
JPS5713945B2 (ja
Inventor
Meison Biin Buratsudofuoodo
Niiru Rangusuton Keisu
Reen Paatoritsuji Richiyaado
Koo Shi Jiiannbon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5476042A publication Critical patent/JPS5476042A/ja
Publication of JPS5713945B2 publication Critical patent/JPS5713945B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
JP12368378A 1977-11-28 1978-10-09 Multiple processor system Granted JPS5476042A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/855,485 US4142234A (en) 1977-11-28 1977-11-28 Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system

Publications (2)

Publication Number Publication Date
JPS5476042A true JPS5476042A (en) 1979-06-18
JPS5713945B2 JPS5713945B2 (ja) 1982-03-20

Family

ID=25321369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12368378A Granted JPS5476042A (en) 1977-11-28 1978-10-09 Multiple processor system

Country Status (6)

Country Link
US (1) US4142234A (ja)
JP (1) JPS5476042A (ja)
DE (1) DE2847960A1 (ja)
FR (1) FR2410335A1 (ja)
GB (1) GB1586847A (ja)
IT (1) IT1160070B (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724086A (en) * 1980-07-16 1982-02-08 Fujitsu Ltd Repealing cotrol system of buffer memory

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5849945B2 (ja) * 1977-12-29 1983-11-08 富士通株式会社 バツフア合せ方式
US4228503A (en) * 1978-10-02 1980-10-14 Sperry Corporation Multiplexed directory for dedicated cache memory system
JPS55134459A (en) * 1979-04-06 1980-10-20 Hitachi Ltd Data processing system
CA1187198A (en) * 1981-06-15 1985-05-14 Takashi Chiba System for controlling access to channel buffers
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
US4484267A (en) * 1981-12-30 1984-11-20 International Business Machines Corporation Cache sharing control in a multiprocessor
US4504902A (en) * 1982-03-25 1985-03-12 At&T Bell Laboratories Cache arrangement for direct memory access block transfer
US4571674A (en) * 1982-09-27 1986-02-18 International Business Machines Corporation Peripheral storage system having multiple data transfer rates
DE3582506D1 (de) * 1984-02-10 1991-05-23 Prime Computer Inc Cache-kohaerenz-anordnung.
US4747043A (en) * 1984-02-10 1988-05-24 Prime Computer, Inc. Multiprocessor cache coherence system
US4638431A (en) * 1984-09-17 1987-01-20 Nec Corporation Data processing system for vector processing having a cache invalidation control unit
FR2571163B1 (fr) * 1984-09-28 1989-02-10 Nec Corp Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.
US5734871A (en) * 1985-10-29 1998-03-31 Mitem Corporation Method for and apparatus for controlling the execution of host computer application programs through a second computer
FR2590699B1 (fr) * 1985-11-25 1994-07-01 Nec Corp Systeme assurant la coherence pour les contenus d'une antememoire
JPS62147548A (ja) * 1985-12-23 1987-07-01 Mitsubishi Electric Corp 外部記憶制御装置
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5107419A (en) * 1987-12-23 1992-04-21 International Business Machines Corporation Method of assigning retention and deletion criteria to electronic documents stored in an interactive information handling system
DE3919802C2 (de) * 1988-06-17 1997-01-30 Hitachi Ltd Speichersteuersystem für ein Multiprozessorsystem
US5058006A (en) * 1988-06-27 1991-10-15 Digital Equipment Corporation Method and apparatus for filtering invalidate requests
EP0349123B1 (en) * 1988-06-27 1995-09-20 Digital Equipment Corporation Multi-processor computer systems having shared memory and private cache memories
US5247688A (en) * 1988-10-14 1993-09-21 Ricoh Company, Ltd. Character recognition sorting apparatus having comparators for simultaneous comparison of data and corresponding key against respective multistage shift arrays
US5226146A (en) * 1988-10-28 1993-07-06 Hewlett-Packard Company Duplicate tag store purge queue
EP0366323A3 (en) * 1988-10-28 1991-09-18 Apollo Computer Inc. Duplicate tag store purge queue
US5163142A (en) * 1988-10-28 1992-11-10 Hewlett-Packard Company Efficient cache write technique through deferred tag modification
US5185875A (en) * 1989-01-27 1993-02-09 Digital Equipment Corporation Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
US5210848A (en) * 1989-02-22 1993-05-11 International Business Machines Corporation Multi-processor caches with large granularity exclusivity locking
US5214766A (en) * 1989-04-28 1993-05-25 International Business Machines Corporation Data prefetching based on store information in multi-processor caches
US5230070A (en) * 1989-09-08 1993-07-20 International Business Machines Corporation Access authorization table for multi-processor caches
US5197139A (en) * 1990-04-05 1993-03-23 International Business Machines Corporation Cache management for multi-processor systems utilizing bulk cross-invalidate
US5325510A (en) * 1990-05-25 1994-06-28 Texas Instruments Incorporated Multiprocessor system and architecture with a computation system for minimizing duplicate read requests
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
IE860318L (en) * 1990-10-01 1986-08-05 Digital Equipment Corp System bus for a multi-cache data processing system
JP2641819B2 (ja) * 1990-11-05 1997-08-20 三菱電機株式会社 キャッシュ・コントローラ並びにフォールト・トレラント・コンピュータ及びそのデータ転送方式
US5829030A (en) * 1990-11-05 1998-10-27 Mitsubishi Denki Kabushiki Kaisha System for performing cache flush transactions from interconnected processor modules to paired memory modules
JPH04372037A (ja) * 1991-06-21 1992-12-25 Matsushita Electric Ind Co Ltd システム管理情報設定装置
US5953510A (en) * 1991-09-05 1999-09-14 International Business Machines Corporation Bidirectional data bus reservation priority controls having token logic
US5428761A (en) * 1992-03-12 1995-06-27 Digital Equipment Corporation System for achieving atomic non-sequential multi-word operations in shared memory
US5423008A (en) * 1992-08-03 1995-06-06 Silicon Graphics, Inc. Apparatus and method for detecting the activities of a plurality of processors on a shared bus
US5504874A (en) * 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
US5634081A (en) * 1994-03-01 1997-05-27 Adaptec, Inc. System for starting and completing a data transfer for a subsequently received autotransfer command after receiving a first SCSI data transfer command that is not autotransfer
JPH07334450A (ja) * 1994-06-10 1995-12-22 Mitsubishi Denki Semiconductor Software Kk インタフェイス装置
JPH0816470A (ja) * 1994-07-04 1996-01-19 Hitachi Ltd 並列計算機
US5778437A (en) * 1995-09-25 1998-07-07 International Business Machines Corporation Invalidation bus optimization for multiprocessors using directory-based cache coherence protocols in which an address of a line to be modified is placed on the invalidation bus simultaneously with sending a modify request to the directory
US6892173B1 (en) * 1998-03-30 2005-05-10 Hewlett-Packard Development Company, L.P. Analyzing effectiveness of a computer cache by estimating a hit rate based on applying a subset of real-time addresses to a model of the cache
US6651143B2 (en) 2000-12-21 2003-11-18 International Business Machines Corporation Cache management using a buffer for invalidation requests
US9646992B2 (en) * 2015-09-03 2017-05-09 Kabushiki Kaisha Toshiba Semiconductor memory
US9898296B2 (en) 2016-01-08 2018-02-20 International Business Machines Corporation Selective suppression of instruction translation lookaside buffer (ITLB) access
US9354885B1 (en) 2016-01-08 2016-05-31 International Business Machines Corporation Selective suppression of instruction cache-related directory access

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
FR129151A (ja) * 1974-02-09
JPS5440182B2 (ja) * 1974-02-26 1979-12-01
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4084234A (en) * 1977-02-17 1978-04-11 Honeywell Information Systems Inc. Cache write capacity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724086A (en) * 1980-07-16 1982-02-08 Fujitsu Ltd Repealing cotrol system of buffer memory
JPS6349257B2 (ja) * 1980-07-16 1988-10-04 Fujitsu Ltd

Also Published As

Publication number Publication date
IT7829733A0 (it) 1978-11-14
IT1160070B (it) 1987-03-04
FR2410335A1 (fr) 1979-06-22
FR2410335B1 (ja) 1984-09-28
DE2847960C2 (ja) 1987-01-29
JPS5713945B2 (ja) 1982-03-20
DE2847960A1 (de) 1979-05-31
GB1586847A (en) 1981-03-25
US4142234A (en) 1979-02-27

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