FR2571163B1 - Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire. - Google Patents

Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.

Info

Publication number
FR2571163B1
FR2571163B1 FR8414964A FR8414964A FR2571163B1 FR 2571163 B1 FR2571163 B1 FR 2571163B1 FR 8414964 A FR8414964 A FR 8414964A FR 8414964 A FR8414964 A FR 8414964A FR 2571163 B1 FR2571163 B1 FR 2571163B1
Authority
FR
France
Prior art keywords
control assembly
value control
data processing
processing system
call value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8414964A
Other languages
English (en)
Other versions
FR2571163A1 (fr
Inventor
Hiroyuki Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to FR8414964A priority Critical patent/FR2571163B1/fr
Publication of FR2571163A1 publication Critical patent/FR2571163A1/fr
Application granted granted Critical
Publication of FR2571163B1 publication Critical patent/FR2571163B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR8414964A 1984-09-28 1984-09-28 Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire. Expired FR2571163B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8414964A FR2571163B1 (fr) 1984-09-28 1984-09-28 Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8414964A FR2571163B1 (fr) 1984-09-28 1984-09-28 Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.

Publications (2)

Publication Number Publication Date
FR2571163A1 FR2571163A1 (fr) 1986-04-04
FR2571163B1 true FR2571163B1 (fr) 1989-02-10

Family

ID=9308191

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8414964A Expired FR2571163B1 (fr) 1984-09-28 1984-09-28 Systeme de traitement de donnees pour traitement de vecteurs ayant un ensemble de commande d'invalidation d'antememoire.

Country Status (1)

Country Link
FR (1) FR2571163B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3618040A (en) * 1968-09-18 1971-11-02 Hitachi Ltd Memory control apparatus in multiprocessor system
US3979726A (en) * 1974-04-10 1976-09-07 Honeywell Information Systems, Inc. Apparatus for selectively clearing a cache store in a processor having segmentation and paging
US4142234A (en) * 1977-11-28 1979-02-27 International Business Machines Corporation Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system

Also Published As

Publication number Publication date
FR2571163A1 (fr) 1986-04-04

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Legal Events

Date Code Title Description
ST Notification of lapse