FR2687812B1 - Systeme de traitement de l'information. - Google Patents

Systeme de traitement de l'information.

Info

Publication number
FR2687812B1
FR2687812B1 FR9301994A FR9301994A FR2687812B1 FR 2687812 B1 FR2687812 B1 FR 2687812B1 FR 9301994 A FR9301994 A FR 9301994A FR 9301994 A FR9301994 A FR 9301994A FR 2687812 B1 FR2687812 B1 FR 2687812B1
Authority
FR
France
Prior art keywords
information processing
processing system
information
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9301994A
Other languages
English (en)
Other versions
FR2687812A1 (fr
Inventor
Hitoshi C O Nec Corpora Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2687812A1 publication Critical patent/FR2687812A1/fr
Application granted granted Critical
Publication of FR2687812B1 publication Critical patent/FR2687812B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR9301994A 1992-02-21 1993-02-22 Systeme de traitement de l'information. Expired - Fee Related FR2687812B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03519892A JP3219826B2 (ja) 1992-02-21 1992-02-21 情報処理装置

Publications (2)

Publication Number Publication Date
FR2687812A1 FR2687812A1 (fr) 1993-08-27
FR2687812B1 true FR2687812B1 (fr) 1997-12-12

Family

ID=12435172

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9301994A Expired - Fee Related FR2687812B1 (fr) 1992-02-21 1993-02-22 Systeme de traitement de l'information.

Country Status (3)

Country Link
US (1) US5481688A (fr)
JP (1) JP3219826B2 (fr)
FR (1) FR2687812B1 (fr)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182239A (ja) * 1993-12-24 1995-07-21 Nec Corp セグメント分割管理システム
JP4058118B2 (ja) * 1994-11-15 2008-03-05 株式会社日立製作所 プログラム生成システム及び方法
US5710724A (en) * 1995-04-20 1998-01-20 Digital Equipment Corp. Dynamic computer performance monitor
US20060015780A1 (en) * 1995-10-25 2006-01-19 Cityu Research Limited Specifying data timeliness requirement and trap enabling on instruction operands of a processor
US5920881A (en) * 1997-05-20 1999-07-06 Micron Electronics, Inc. Method and system for using a virtual register file in system memory
US6192457B1 (en) 1997-07-02 2001-02-20 Micron Technology, Inc. Method for implementing a graphic address remapping table as a virtual register file in system memory
US6195734B1 (en) 1997-07-02 2001-02-27 Micron Technology, Inc. System for implementing a graphic address remapping table as a virtual register file in system memory
US6108733A (en) * 1998-01-20 2000-08-22 Micron Technology, Inc. Method for extending the available number of configuration registers
US6243775B1 (en) 1998-01-20 2001-06-05 Micron Technology, Inc. System for extending the available number of configuration registers
US6272576B1 (en) 1998-01-20 2001-08-07 Micron Technology, Inc. Method for extending the available number of configuration registers
US6223271B1 (en) 1998-07-15 2001-04-24 Compaq Computer Corp. System and method for detecting system memory size using ROM based paging tables
US7685400B2 (en) 2004-12-15 2010-03-23 International Business Machines Corporation Storage of data blocks of logical volumes in a virtual disk storage subsystem
US7581074B2 (en) * 2006-05-19 2009-08-25 International Business Machines Corporation Facilitating use of storage access keys to access storage
US7594094B2 (en) * 2006-05-19 2009-09-22 International Business Machines Corporation Move data facility with optional specifications
US8924685B2 (en) * 2010-05-11 2014-12-30 Qualcomm Incorporated Configuring surrogate memory accessing agents using non-priviledged processes
US10656945B2 (en) * 2012-06-15 2020-05-19 International Business Machines Corporation Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction
US9524248B2 (en) * 2012-07-18 2016-12-20 Micron Technology, Inc. Memory management for a hierarchical memory system
WO2018154494A1 (fr) 2017-02-23 2018-08-30 Cerebras Systems Inc. Apprentissage profond accéléré
US11488004B2 (en) 2017-04-17 2022-11-01 Cerebras Systems Inc. Neuron smearing for accelerated deep learning
EP3607503B1 (fr) 2017-04-17 2022-03-09 Cerebras Systems Inc. Activation de tâche pour un apprentissage profond accéléré
WO2018193353A1 (fr) 2017-04-17 2018-10-25 Cerebras Systems Inc. Étalement de neurones pour apprentissage profond accéléré
JP7132491B2 (ja) 2018-05-14 2022-09-07 富士通株式会社 メモリ制御装置、メモリ制御プログラムおよびメモリ制御方法
WO2020044152A1 (fr) 2018-08-28 2020-03-05 Cerebras Systems Inc. Textile informatique mis à l'échelle pour apprentissage profond accéléré
US11328208B2 (en) 2018-08-29 2022-05-10 Cerebras Systems Inc. Processor element redundancy for accelerated deep learning
WO2020044208A1 (fr) 2018-08-29 2020-03-05 Cerebras Systems Inc. Améliorations apportées à une architecture de jeu d'instructions (isa) pour un apprentissage profond accéléré

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400729A1 (fr) * 1977-08-17 1979-03-16 Cii Honeywell Bull Dispositif pour la transformation d'adresses virtuelles en adresses physiques dans un systeme de traitement de donnees
US4476524A (en) * 1981-07-02 1984-10-09 International Business Machines Corporation Page storage control methods and means
JPS60126749A (ja) * 1983-12-14 1985-07-06 Hitachi Ltd メモリ制御方式
US4669043A (en) * 1984-02-17 1987-05-26 Signetics Corporation Memory access controller
JPS6261132A (ja) * 1985-09-12 1987-03-17 Fujitsu Ltd デ−タ転送命令制御方式
US5347636A (en) * 1985-11-08 1994-09-13 Nec Corporation Data processor which efficiently accesses main memory and input/output devices
US5233700A (en) * 1987-03-03 1993-08-03 Nec Corporation Address translation device with an address translation buffer loaded with presence bits
JPS63244152A (ja) * 1987-03-30 1988-10-11 Fujitsu Ltd 拡張記憶装置アクセス制御装置
JP2668438B2 (ja) * 1989-04-21 1997-10-27 三菱電機株式会社 データ検索装置
FR2652926B1 (fr) * 1989-10-06 1994-07-08 Bull Sa Procede d'exploitation de la memoire dans un systeme informatique du type a adressage virtuel et dispositif pour la mise en óoeuvre dudit procede.
US5237668A (en) * 1989-10-20 1993-08-17 International Business Machines Corporation Process using virtual addressing in a non-privileged instruction to control the copying of a page of data in or between multiple media

Also Published As

Publication number Publication date
US5481688A (en) 1996-01-02
JP3219826B2 (ja) 2001-10-15
JPH05233452A (ja) 1993-09-10
FR2687812A1 (fr) 1993-08-27

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Legal Events

Date Code Title Description
ST Notification of lapse