JPS5476030A - Input/output channel device - Google Patents

Input/output channel device

Info

Publication number
JPS5476030A
JPS5476030A JP14373077A JP14373077A JPS5476030A JP S5476030 A JPS5476030 A JP S5476030A JP 14373077 A JP14373077 A JP 14373077A JP 14373077 A JP14373077 A JP 14373077A JP S5476030 A JPS5476030 A JP S5476030A
Authority
JP
Japan
Prior art keywords
data
input
channel device
memory
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14373077A
Other languages
Japanese (ja)
Inventor
Takeshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14373077A priority Critical patent/JPS5476030A/en
Publication of JPS5476030A publication Critical patent/JPS5476030A/en
Pending legal-status Critical Current

Links

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE: To increase the memory throughput for the input/output channel device containing the buffer memory by replacing the data transfer action within the channel device to the high-speed inter-register action.
CONSTITUTION: In case the channel performs the writing action in the data transfer control to the memory for the channel device, the data is transferred from the memory via data bus MDTB1 which connects the memory and the channel device. And the data is ratched to register MIR10 through selector 40 and then shifted to register MOR12. In other words, the writing to buffer BFR14 for the data storage use is carried out through MOR12. Then the data stored in BFR14 is read out to register DOR71 which is connected to the interface to transmit the data to the input/output device from the channel device and then transferred to the input/ output device via the input/output interface.
COPYRIGHT: (C)1979,JPO&Japio
JP14373077A 1977-11-30 1977-11-30 Input/output channel device Pending JPS5476030A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14373077A JPS5476030A (en) 1977-11-30 1977-11-30 Input/output channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14373077A JPS5476030A (en) 1977-11-30 1977-11-30 Input/output channel device

Publications (1)

Publication Number Publication Date
JPS5476030A true JPS5476030A (en) 1979-06-18

Family

ID=15345663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14373077A Pending JPS5476030A (en) 1977-11-30 1977-11-30 Input/output channel device

Country Status (1)

Country Link
JP (1) JPS5476030A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100939A (en) * 1973-07-30 1975-08-11
JPS5145942A (en) * 1974-10-17 1976-04-19 Omron Tateisi Electronics Co

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50100939A (en) * 1973-07-30 1975-08-11
JPS5145942A (en) * 1974-10-17 1976-04-19 Omron Tateisi Electronics Co

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