JPS5466730A - Input processor for sequence controller - Google Patents

Input processor for sequence controller

Info

Publication number
JPS5466730A
JPS5466730A JP13380377A JP13380377A JPS5466730A JP S5466730 A JPS5466730 A JP S5466730A JP 13380377 A JP13380377 A JP 13380377A JP 13380377 A JP13380377 A JP 13380377A JP S5466730 A JPS5466730 A JP S5466730A
Authority
JP
Japan
Prior art keywords
input signal
correct
condition
control
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13380377A
Other languages
Japanese (ja)
Inventor
Yasuo Goshima
Tatsuro Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13380377A priority Critical patent/JPS5466730A/en
Publication of JPS5466730A publication Critical patent/JPS5466730A/en
Pending legal-status Critical Current

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Landscapes

  • Programmable Controllers (AREA)

Abstract

PURPOSE: To enable to perform correct and speedy control, by receiving the condition of the input signal at each read-in timing outputted from the memory, judging correct condition, and feeding only the input signal judged as correct to the control and operation section.
CONSTITUTION: In performing the operational processing using the digital computer, the scanning memory 20 memorizes at least the condition of input signal at three read-in timings. Further, the judging circuit 30 receiving the condition of the input signal at each read-in timing outputted from the memory 20 and judging the correct condition of the input signal is provided. Thus, by giving only the input signal judged as correct from the circuit 30 to the control operation section 40, correct and speedy control can be made.
COPYRIGHT: (C)1979,JPO&Japio
JP13380377A 1977-11-08 1977-11-08 Input processor for sequence controller Pending JPS5466730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13380377A JPS5466730A (en) 1977-11-08 1977-11-08 Input processor for sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13380377A JPS5466730A (en) 1977-11-08 1977-11-08 Input processor for sequence controller

Publications (1)

Publication Number Publication Date
JPS5466730A true JPS5466730A (en) 1979-05-29

Family

ID=15113389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13380377A Pending JPS5466730A (en) 1977-11-08 1977-11-08 Input processor for sequence controller

Country Status (1)

Country Link
JP (1) JPS5466730A (en)

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