JPS5465415A - Time matching circuit - Google Patents

Time matching circuit

Info

Publication number
JPS5465415A
JPS5465415A JP13146377A JP13146377A JPS5465415A JP S5465415 A JPS5465415 A JP S5465415A JP 13146377 A JP13146377 A JP 13146377A JP 13146377 A JP13146377 A JP 13146377A JP S5465415 A JPS5465415 A JP S5465415A
Authority
JP
Japan
Prior art keywords
signal
reference signal
shifted
compared
matching circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13146377A
Other languages
Japanese (ja)
Inventor
Tsunayoshi Shimoyama
Toshiyuki Morita
Toshiharu Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13146377A priority Critical patent/JPS5465415A/en
Publication of JPS5465415A publication Critical patent/JPS5465415A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To ensure an automatic adjustment for the bit time of the 2-series signals of the same signal source and different route in the radio PCM transmission by comparing the shift output of the input signal and the reference signal. CONSTITUTION:Adjusted signal DATA is shifted automatically by one bit through shift register 12, and one of he shifted signals is compared (18) with the reference signal which passed through delay circuit 13. If no coincidence is obtained in the above comparison, another signal shifted automatically is compared (18) with the reference signal again. With repetition of this action, the coincident signal is delivered.
JP13146377A 1977-11-04 1977-11-04 Time matching circuit Pending JPS5465415A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13146377A JPS5465415A (en) 1977-11-04 1977-11-04 Time matching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13146377A JPS5465415A (en) 1977-11-04 1977-11-04 Time matching circuit

Publications (1)

Publication Number Publication Date
JPS5465415A true JPS5465415A (en) 1979-05-26

Family

ID=15058540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13146377A Pending JPS5465415A (en) 1977-11-04 1977-11-04 Time matching circuit

Country Status (1)

Country Link
JP (1) JPS5465415A (en)

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