JPS5644241A - Transmitting and receiving circuit - Google Patents

Transmitting and receiving circuit

Info

Publication number
JPS5644241A
JPS5644241A JP12137579A JP12137579A JPS5644241A JP S5644241 A JPS5644241 A JP S5644241A JP 12137579 A JP12137579 A JP 12137579A JP 12137579 A JP12137579 A JP 12137579A JP S5644241 A JPS5644241 A JP S5644241A
Authority
JP
Japan
Prior art keywords
circuit
receiving
clock
data
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12137579A
Other languages
Japanese (ja)
Inventor
Yoshinori Sugawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12137579A priority Critical patent/JPS5644241A/en
Publication of JPS5644241A publication Critical patent/JPS5644241A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Abstract

PURPOSE:To reduce the number of circuits, by using the transmission circuit and the receiving circuit in common for forward communication and backward communication. CONSTITUTION:When selection indication signal line 11 is set to ''1'', forward clock 5 and backward clock 6 are sent to transmission circuit 7 and receiving circuit 8 respectively by clock selecting circuit 9, and transmission data and receiving data from backward receiving data line BRD are sent to forward transmission data line SD and receiving data 8 respectively by data selecting circuit 10. Next, when selection indication signal line 11 is set to ''0'', backward clock 6 and forward clock 5 are sent to transmission circuit 7 and receiving circuit 8 respectively by clock selecting circuit 9, and transmission data and receiving data from forward receiving data line RD are sent to backward transmission data line BSD and receiving circuit 8 respectively by data selecting circuit 10.
JP12137579A 1979-09-20 1979-09-20 Transmitting and receiving circuit Pending JPS5644241A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12137579A JPS5644241A (en) 1979-09-20 1979-09-20 Transmitting and receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12137579A JPS5644241A (en) 1979-09-20 1979-09-20 Transmitting and receiving circuit

Publications (1)

Publication Number Publication Date
JPS5644241A true JPS5644241A (en) 1981-04-23

Family

ID=14809666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12137579A Pending JPS5644241A (en) 1979-09-20 1979-09-20 Transmitting and receiving circuit

Country Status (1)

Country Link
JP (1) JPS5644241A (en)

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