JPS5464960A - Carrier wave regenerator circuit - Google Patents
Carrier wave regenerator circuitInfo
- Publication number
- JPS5464960A JPS5464960A JP13179277A JP13179277A JPS5464960A JP S5464960 A JPS5464960 A JP S5464960A JP 13179277 A JP13179277 A JP 13179277A JP 13179277 A JP13179277 A JP 13179277A JP S5464960 A JPS5464960 A JP S5464960A
- Authority
- JP
- Japan
- Prior art keywords
- output
- phase
- add
- sent
- carrier wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
Abstract
PURPOSE:To ensuer an assured lead-in of the regenerated carrier wave to the prescribed phase by controlling the control voltage of the voltage control oscillator which has the phase synchronization with the input signal of the orthogonal partial response modulated wave via the switch which selects phase detection output. CONSTITUTION:The orthogonal partial response modulated wave sent from input terminal IN is applied to phase detector PD1 and PD2, and the phase detection is given by the output carrier wave of voltage control oscillator VCO. In this case, the carrier waves featuring the 90 deg.-phase difference is applied to PD1 and PD2 through 90 deg.-phase shifter PHS. This output is then applied to logic circuit LG plus delay circuit DL1 and DL2. The output of DL1 is branched off into two: one is sent to adder ADD via inverter INV1 and switch SW1, and the other is sent also to ADD via SW2. In the same way, one of the output of DL2 is applied to ADD via SW3 and the other is applied to ADD via inverter INV2 respectively. The output of ADD is fed back to oscillator VCO via low pass filter LPF.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13179277A JPS5464960A (en) | 1977-11-02 | 1977-11-02 | Carrier wave regenerator circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13179277A JPS5464960A (en) | 1977-11-02 | 1977-11-02 | Carrier wave regenerator circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5464960A true JPS5464960A (en) | 1979-05-25 |
Family
ID=15066231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13179277A Pending JPS5464960A (en) | 1977-11-02 | 1977-11-02 | Carrier wave regenerator circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5464960A (en) |
-
1977
- 1977-11-02 JP JP13179277A patent/JPS5464960A/en active Pending
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