JPS5463617A - Input circuit - Google Patents

Input circuit

Info

Publication number
JPS5463617A
JPS5463617A JP12661477A JP12661477A JPS5463617A JP S5463617 A JPS5463617 A JP S5463617A JP 12661477 A JP12661477 A JP 12661477A JP 12661477 A JP12661477 A JP 12661477A JP S5463617 A JPS5463617 A JP S5463617A
Authority
JP
Japan
Prior art keywords
input
output
informaton
gate
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12661477A
Other languages
Japanese (ja)
Inventor
Osamu Kondo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12661477A priority Critical patent/JPS5463617A/en
Publication of JPS5463617A publication Critical patent/JPS5463617A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to output a stable logical level with preventing the increment of power consumption dependent upon input levels by applying control signals so that the output may be obtained synchronously with input informaton.
CONSTITUTION: Input terminal 1 of inverter circuit 10 and output terminal 3' of input switch KI have the drain or suce electrode of P-chFETQP4 connected; and at the period when control signals S is applied to the gate, QP4 is turned on and input information can be obtained from output terminal 2 of circuit 10. Meanwhile, at the period when signal S is not applied to the gate, QP4 is turned off and input informaton is inhibited from being taken out. Then, the current across QP4 and N- chFETQN3 does not flow. As a result, average power consumption can be reduced.
COPYRIGHT: (C)1979,JPO&Japio
JP12661477A 1977-10-20 1977-10-20 Input circuit Pending JPS5463617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12661477A JPS5463617A (en) 1977-10-20 1977-10-20 Input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12661477A JPS5463617A (en) 1977-10-20 1977-10-20 Input circuit

Publications (1)

Publication Number Publication Date
JPS5463617A true JPS5463617A (en) 1979-05-22

Family

ID=14939552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12661477A Pending JPS5463617A (en) 1977-10-20 1977-10-20 Input circuit

Country Status (1)

Country Link
JP (1) JPS5463617A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155536U (en) * 1980-04-18 1981-11-20
JPS60198920A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Interface circuit
JPH0228147U (en) * 1988-08-12 1990-02-23

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155536U (en) * 1980-04-18 1981-11-20
JPS60198920A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Interface circuit
JPH0228147U (en) * 1988-08-12 1990-02-23

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