JPS5462734A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5462734A
JPS5462734A JP12926777A JP12926777A JPS5462734A JP S5462734 A JPS5462734 A JP S5462734A JP 12926777 A JP12926777 A JP 12926777A JP 12926777 A JP12926777 A JP 12926777A JP S5462734 A JPS5462734 A JP S5462734A
Authority
JP
Japan
Prior art keywords
memory
writing
signal
bit
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12926777A
Other languages
Japanese (ja)
Inventor
Takashi Hiraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12926777A priority Critical patent/JPS5462734A/en
Publication of JPS5462734A publication Critical patent/JPS5462734A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To shorten an access time by simplifying the procedure of partial writing, and to reduce the size of the hardware of a board and work load, by enabling the memory board to function to write partially data to the memory by itself. CONSTITUTION:At the time to writing to the 16-bit memroy partitioned into two 8-bit memroy blocks 11 snd 12, a signal controlling a memory address and memory operation and write data are both transmitted to the memory in sequence via lines 17 and 16, and 14 and 15, and at the time of simultaneous partial writing to the memory, its request signal is sent out to the memory via line 19 and partial write control circuit 13 in the memory board, after receiving signal 19, fetches a bit assignig blocks 11 and 12 from signal 17 and decodes it. On the other hand, since circuit 13 has received one control signal needed for writing fro line 18, either block 11 or 12 is chosen judging from this received control signal and the result of decoding, and data 14 and 15 from the CPU are written to the selected one.
JP12926777A 1977-10-28 1977-10-28 Memory control system Pending JPS5462734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12926777A JPS5462734A (en) 1977-10-28 1977-10-28 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12926777A JPS5462734A (en) 1977-10-28 1977-10-28 Memory control system

Publications (1)

Publication Number Publication Date
JPS5462734A true JPS5462734A (en) 1979-05-21

Family

ID=15005341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12926777A Pending JPS5462734A (en) 1977-10-28 1977-10-28 Memory control system

Country Status (1)

Country Link
JP (1) JPS5462734A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123526A (en) * 1973-03-30 1974-11-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49123526A (en) * 1973-03-30 1974-11-26

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