JPS5456734A - Intermediate buffer memory control system - Google Patents
Intermediate buffer memory control systemInfo
- Publication number
- JPS5456734A JPS5456734A JP12329077A JP12329077A JPS5456734A JP S5456734 A JPS5456734 A JP S5456734A JP 12329077 A JP12329077 A JP 12329077A JP 12329077 A JP12329077 A JP 12329077A JP S5456734 A JPS5456734 A JP S5456734A
- Authority
- JP
- Japan
- Prior art keywords
- block
- memory
- data
- buffer memory
- intermediate buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To eliminate installation of the extra auxiliary memory by providing the block which can store the data of the address belonging to the faulty block at the intermediate buffer memory in case some fault occurs in a certain block of the main memory.
CONSTITUTION: In the memory system of the set associative method as shown in the diagram, the data of a certain block B in main memory 3 is transferred to the same set block B between intermediate buffer memory 2 and both-buffer memory 1. In case some fault is detected in a certain block BE within main memory 3, block BE' which can store the data of the address belonging to block BE into memory 2 is opened forcedly even though no request is given from CPU. After this, the replacement is inhibited for the data of block BE'. The data transfer is carried out via memory 2 between main memory 3 and file 5, so faulty block BE in memory 3 is never used after opening of block BE', in memory 2
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12329077A JPS5456734A (en) | 1977-10-14 | 1977-10-14 | Intermediate buffer memory control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12329077A JPS5456734A (en) | 1977-10-14 | 1977-10-14 | Intermediate buffer memory control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5456734A true JPS5456734A (en) | 1979-05-08 |
Family
ID=14856880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12329077A Pending JPS5456734A (en) | 1977-10-14 | 1977-10-14 | Intermediate buffer memory control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5456734A (en) |
-
1977
- 1977-10-14 JP JP12329077A patent/JPS5456734A/en active Pending
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