JPS5454511A - Frame phase synchronism circuit - Google Patents

Frame phase synchronism circuit

Info

Publication number
JPS5454511A
JPS5454511A JP12169677A JP12169677A JPS5454511A JP S5454511 A JPS5454511 A JP S5454511A JP 12169677 A JP12169677 A JP 12169677A JP 12169677 A JP12169677 A JP 12169677A JP S5454511 A JPS5454511 A JP S5454511A
Authority
JP
Japan
Prior art keywords
frame
signal
synchronism
frame phase
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12169677A
Other languages
Japanese (ja)
Inventor
Yozo Fujisaki
Shuzo Morita
Hidetoshi Shirakawa
Moriyuki Yamamoto
Susumu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP12169677A priority Critical patent/JPS5454511A/en
Publication of JPS5454511A publication Critical patent/JPS5454511A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To perform giving and receiving the signal after the control only with initial setting of the frame phase synchronism, by discriminating the phase difference with the reference frame through the use of the gate circuit, AND gates and FF's from the pattern of the frame phase identifying signal and by controlling the amount of delay. CONSTITUTION:At the reception side unit RD performing giving and receiving the digital signal according to the timing signal fed from the same timing generating unit TMG, the reception digital signal is delayed with the delay circuit DL. Further, the frame phase identifying signal inserted in the specific location in the frame of the digital signal is read out from the circuit DL in the timing of the frame phase signal, the phase difference with the reference frame is discriminated by using the gate circuits G1...G5, AND gates A1...A4 and flip flop's FF1...FF4 with the pattern of the frame synchronism identifying signal, controlling the amount of delay of the circuit DL. Thus, only with initial setting of the frame phase synchronism, the giving and reception of digital signal can be made without out of synchronism for the frame phase synchronism after that.
JP12169677A 1977-10-11 1977-10-11 Frame phase synchronism circuit Pending JPS5454511A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12169677A JPS5454511A (en) 1977-10-11 1977-10-11 Frame phase synchronism circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12169677A JPS5454511A (en) 1977-10-11 1977-10-11 Frame phase synchronism circuit

Publications (1)

Publication Number Publication Date
JPS5454511A true JPS5454511A (en) 1979-04-28

Family

ID=14817608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12169677A Pending JPS5454511A (en) 1977-10-11 1977-10-11 Frame phase synchronism circuit

Country Status (1)

Country Link
JP (1) JPS5454511A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102040860B1 (en) 2018-07-05 2019-11-05 주식회사 유니크 Solenoid actuator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102040860B1 (en) 2018-07-05 2019-11-05 주식회사 유니크 Solenoid actuator

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