JPS5451740A - Interface control circuit - Google Patents

Interface control circuit

Info

Publication number
JPS5451740A
JPS5451740A JP11881377A JP11881377A JPS5451740A JP S5451740 A JPS5451740 A JP S5451740A JP 11881377 A JP11881377 A JP 11881377A JP 11881377 A JP11881377 A JP 11881377A JP S5451740 A JPS5451740 A JP S5451740A
Authority
JP
Japan
Prior art keywords
input
output terminals
transmission line
data transmission
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11881377A
Other languages
Japanese (ja)
Inventor
Akira Yasuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP11881377A priority Critical patent/JPS5451740A/en
Publication of JPS5451740A publication Critical patent/JPS5451740A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To ensure the data transmission of the input and the output via the common data transmission line by producing the control signal to decide the data transmission direction based on the set pulse, and thus to realize the cost reduction.
CONSTITUTION: First and second interface control part 3 and 4 are combined via data transmission line l composed of 4 lines collected into one set which also connects data input/output terminals B0WB3 and B'0WB'3. At the same time, data input and output terminals S0WS3 and R0WR3of computer 1 are connected to input and output terminals S'0WS'3 and R'0WR'3 of control part 3 respectively, and input and output terminals BB0WBB3 and RR0WRR3 of terminal unit 2 are connected to input and output terminals BB'1WBB'3 and RR'1WRR'3 of control part 4 respectively. Set pulse ST(a) is applied through terminal L of computer 1, and control signal (b) is produced with the rise of pulse ST and then applied to transmission line lS to control the transmission direction of line l. And ratch signal RS (c) is produced after fixed time TB from the time point of ST application to be applied to terminal LLL via transmission line lR. And the output data given from computer 1 is stored in the ratch memory of terminal unit 2
COPYRIGHT: (C)1979,JPO&Japio
JP11881377A 1977-09-30 1977-09-30 Interface control circuit Pending JPS5451740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11881377A JPS5451740A (en) 1977-09-30 1977-09-30 Interface control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11881377A JPS5451740A (en) 1977-09-30 1977-09-30 Interface control circuit

Publications (1)

Publication Number Publication Date
JPS5451740A true JPS5451740A (en) 1979-04-23

Family

ID=14745761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11881377A Pending JPS5451740A (en) 1977-09-30 1977-09-30 Interface control circuit

Country Status (1)

Country Link
JP (1) JPS5451740A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166525A (en) * 1980-05-26 1981-12-21 Hitachi Ltd Information transferring system in input and output interface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166525A (en) * 1980-05-26 1981-12-21 Hitachi Ltd Information transferring system in input and output interface

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