JPS54118750A - Control system by multi-system processor - Google Patents
Control system by multi-system processorInfo
- Publication number
- JPS54118750A JPS54118750A JP2616578A JP2616578A JPS54118750A JP S54118750 A JPS54118750 A JP S54118750A JP 2616578 A JP2616578 A JP 2616578A JP 2616578 A JP2616578 A JP 2616578A JP S54118750 A JPS54118750 A JP S54118750A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- control output
- output
- control
- decision
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Hardware Redundancy (AREA)
- Multi Processors (AREA)
Abstract
PURPOSE: To ensure the accelerated switching as well as to increase the control reliability for the general reliable apparatus through automatic selection of the processor to be used to control the intermediate or low reliability apparatus by utilizing the coincident decision result of the control output of each processor.
CONSTITUTION: Decision-by-majority circuit 10 supplies the decision-by-majority signals of processor 1, 2 and 3 to high reliability apparatus 4. Coincidence deciding circuit 11 receives 1st control output 7a, 8a and 9a for apparatus 4 from processor 1, 2 and 3, and then delivers the coincidence signal via lead wire 12 in case output 7a is in agreement with the 1st control output and via wire 13 and 14 when output 8a or 9a coincides with another 1st control output respectively. Selector circuit 15 delivers the coincidence signal of two output corresponding to each other among 2nd control output 8b, 9b and 9c given from processor 1, 2 and 3 to intermediate reliability apparatus 5 when the signals are transmitted from all or two of wires 12, 13 and 14. Selector circuit 16 selects one of 3rd control output 7c, 8c and 9c and supplies it to low reliability apparatus 6 wit supply of the input signal through either two of wires 12, 13 and 14.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53026165A JPS5939780B2 (en) | 1978-03-08 | 1978-03-08 | Control device using multi-system processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53026165A JPS5939780B2 (en) | 1978-03-08 | 1978-03-08 | Control device using multi-system processing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54118750A true JPS54118750A (en) | 1979-09-14 |
JPS5939780B2 JPS5939780B2 (en) | 1984-09-26 |
Family
ID=12185930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53026165A Expired JPS5939780B2 (en) | 1978-03-08 | 1978-03-08 | Control device using multi-system processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5939780B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60263252A (en) * | 1984-06-11 | 1985-12-26 | Japanese National Railways<Jnr> | Processing, collating and outputting method of multisystem |
-
1978
- 1978-03-08 JP JP53026165A patent/JPS5939780B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60263252A (en) * | 1984-06-11 | 1985-12-26 | Japanese National Railways<Jnr> | Processing, collating and outputting method of multisystem |
Also Published As
Publication number | Publication date |
---|---|
JPS5939780B2 (en) | 1984-09-26 |
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