JPS56157554A - Microcomputer device - Google Patents

Microcomputer device

Info

Publication number
JPS56157554A
JPS56157554A JP5989280A JP5989280A JPS56157554A JP S56157554 A JPS56157554 A JP S56157554A JP 5989280 A JP5989280 A JP 5989280A JP 5989280 A JP5989280 A JP 5989280A JP S56157554 A JPS56157554 A JP S56157554A
Authority
JP
Japan
Prior art keywords
rom6
address
signal
logical
becomes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5989280A
Other languages
Japanese (ja)
Inventor
Kazushi Mizukami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5989280A priority Critical patent/JPS56157554A/en
Publication of JPS56157554A publication Critical patent/JPS56157554A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection

Abstract

PURPOSE:To extend the system efficiently by connecting slave devices, by supplying signals, which indicate address areas used by slave devices, from slave devices to a master device. CONSTITUTION:If an address of an ROM6 is selected when a slave device 5 is not connected, an address decode signal 9 and an address area signal 14 of a master device 4 are logical 1 together, and the signal of logical 0 is supplied to a chip select terminal 7 of the ROM6, and therefore, the ROM6 becomes operatable. If an address of ROM6 is selected when the device 5 is connected, the signal 9 becomes logical 1; however, since an RAM13 of the device 5 has the same address arrangement, it is selected simultaneously, and a signal 14 becomes logical 0. Then, the input of the terminal 7 becomes logical 1 to inhibit the operation of the ROM6, and the RAM13 is arranged in the arrangement address area of this ROM6 and becomes operatable. As the result, when the device 5 is connected, the system with the RAM13 added is obtained.
JP5989280A 1980-05-08 1980-05-08 Microcomputer device Pending JPS56157554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5989280A JPS56157554A (en) 1980-05-08 1980-05-08 Microcomputer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5989280A JPS56157554A (en) 1980-05-08 1980-05-08 Microcomputer device

Publications (1)

Publication Number Publication Date
JPS56157554A true JPS56157554A (en) 1981-12-04

Family

ID=13126213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5989280A Pending JPS56157554A (en) 1980-05-08 1980-05-08 Microcomputer device

Country Status (1)

Country Link
JP (1) JPS56157554A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347484A1 (en) * 1988-06-24 1989-12-27 Robert Bosch Gmbh Microcomputer having selectable datestorage
EP0443876A2 (en) * 1990-02-23 1991-08-28 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0347484A1 (en) * 1988-06-24 1989-12-27 Robert Bosch Gmbh Microcomputer having selectable datestorage
EP0443876A2 (en) * 1990-02-23 1991-08-28 Kabushiki Kaisha Toshiba Computer system capable of connecting expansion unit
US5299322A (en) * 1990-02-23 1994-03-29 Kabushiki Kaisha Toshiba Computer system with improved interface control of an I/O expansion unit

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