JPS57120282A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS57120282A
JPS57120282A JP419081A JP419081A JPS57120282A JP S57120282 A JPS57120282 A JP S57120282A JP 419081 A JP419081 A JP 419081A JP 419081 A JP419081 A JP 419081A JP S57120282 A JPS57120282 A JP S57120282A
Authority
JP
Japan
Prior art keywords
memories
input terminals
signals
counter
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP419081A
Other languages
Japanese (ja)
Other versions
JPS6110908B2 (en
Inventor
Mamoru Hatakawa
Masahiko Kitamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP419081A priority Critical patent/JPS57120282A/en
Publication of JPS57120282A publication Critical patent/JPS57120282A/en
Publication of JPS6110908B2 publication Critical patent/JPS6110908B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To achieve desired logical processing which responds to an input signal while eliminating the need for the troublesome modifying operation of external wiring, by outputting input terminal selection signals for memories from a control memory. CONSTITUTION:A logical circuit is provided with a multiplexer 1 which includes switches SW1-SWn that are connected to input terminals AD1-ADn of memories M1-Mm through flip-flops F1-Fn of an addressable latch circuit 6, receive external signals from lines S1-Sl, and supply the received signals to selected input terminals in response to address signals supplied through a counter 4. A selection signal for selecting the input terminals of those memories M1- Mm is outputted from a control memory 7 by receiving the address signal from the counter 4.
JP419081A 1981-01-14 1981-01-14 Logical circuit Granted JPS57120282A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP419081A JPS57120282A (en) 1981-01-14 1981-01-14 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP419081A JPS57120282A (en) 1981-01-14 1981-01-14 Logical circuit

Publications (2)

Publication Number Publication Date
JPS57120282A true JPS57120282A (en) 1982-07-27
JPS6110908B2 JPS6110908B2 (en) 1986-03-31

Family

ID=11577775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP419081A Granted JPS57120282A (en) 1981-01-14 1981-01-14 Logical circuit

Country Status (1)

Country Link
JP (1) JPS57120282A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6137409U (en) * 1984-08-13 1986-03-08 日鍛バルブ株式会社 Hydraulic valve gap automatic correction device

Also Published As

Publication number Publication date
JPS6110908B2 (en) 1986-03-31

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