JP3253770B2 - Test mode setting circuit for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit capable of switching between a normal operation and a test mode by using one test-dedicated terminal and setting various test modes. It relates to a test mode setting circuit .

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a configuration example of a testable integrated circuit. In the figure, A to D are functional blocks, 10A to 10D are test data lines, 11 and 1
Reference numeral 2 denotes a normal data line, and reference numeral 13 denotes a multiplexer (signal switch). The signal A and the test A are applied to the block A. When signal A is on,
Block A operates. An off test A indicates a normal operation, and an on test A indicates a block A test. When the test A is on, the data of the block A is input to the multiplexer 13 via the test data line 10A and sent to the blocks C and B via the normal data line 11. Although not shown, data from an input terminal of the integrated circuit is supplied to the block A via a data line.

A signal C and a test C are applied to a block C. During normal operation, data of block C is input to multiplexer 13 via data line 10C,
Even during the test of the block C, the data of the block C is input to the multiplexer 13 via the data line 10C.

A signal B and a test B are applied to a block B. If test B is on, block B
Is input to the multiplexer 13 via the test data line 10B and the normal data line 12B.
To block D.

[0005] To the block D, a signal D and a test D are applied. During normal operation, data of block D is input to multiplexer 13 via data line 10D,
Also during the test of the block D, the data of the block D is input to the multiplexer 13 via the data line 10D.

The multiplexer 13 outputs data on the data line 10A when the test A is on, outputs data on the data line 10B when the test B is on, and outputs data on the data line 10C when the test C is on. When the test D is on, the data on the data line 10D is output. Note that the test C input to the multiplexer 13 is also turned on when the signal C is on, and the test D input to the multiplexer 13 is also turned on when the signal D is on.

[0007]

In the prior art, a plurality of unused external input terminals were used to set a test mode state for an integrated circuit. However, if there are no unused external input terminals, testing in the same package is not possible, and the package size increases because the unused external input terminals are secured by using a package with a large number of terminals. However, there are problems such as low mounting density, wastefulness, and high price.

In the prior art, in order to keep the integrated circuit in the test mode state, the signal in the test mode state must be continuously input to the dedicated test terminal. Therefore, when a circuit other than the function to be tested is directly connected to the same dedicated test terminal, the circuit other than the function to be tested may be affected. Further, the more complex the integrated circuit, the more test patterns and the longer the time for product testing.

The present invention has been made in view of the above point, and can switch between a normal operation and a test mode by using one test-dedicated terminal, and can use a simple circuit. An object of the present invention is to provide an integrated circuit test mode setting circuit capable of setting various test modes.

[0010]

FIG. 1 is a diagram illustrating the principle of the present invention. The test mode setting circuit for an integrated circuit according to the first aspect of the present invention outputs one test dedicated terminal, one activation terminal, an external output terminal, a plurality of function blocks, and a plurality of test signals. A test-dedicated circuit, and an activation circuit that outputs a plurality of activation signals. When the test signal is on, data of a functional block associated with the test signal is output from an external output terminal. A test mode setting circuit for an integrated circuit in which a function block associated with the activation signal is activated when the activation signal is on, the activation circuit comprising: And an activation decoder circuit for decoding the output of the activation storage means. The output of the activation decoder circuit is used as an activation signal. A test decoder circuit for decoding the output of the test storage means on condition that the output of the test decoder circuit is used as a test signal and an activation instruction voltage is applied to the activation terminal. The input data of the activation storage means is output from the output side of the activation storage means, and when the activation instruction voltage is not applied to the activation terminal, the output data of the activation storage means is fixed. When the test instruction voltage is applied, the input data of the test storage means is output from the output side of the test storage means, and when the test instruction voltage is not applied to the test dedicated terminal, the output data of the test storage means is fixed, The test decoder circuit is enabled when the test instruction voltage is not applied to the test dedicated terminal.

According to a second aspect of the present invention, there is provided a test mode setting circuit for an integrated circuit, wherein one test dedicated terminal, one activation terminal, an external output terminal, a plurality of functional blocks, and a plurality of test terminals are provided. A test circuit for outputting a signal; and an activation circuit for outputting a plurality of activation signals. When the test signal is on, data of a functional block associated with the test signal is output from an external output terminal. A test mode setting circuit for an integrated circuit, wherein when the activation signal is on, the function block associated with the activation signal is activated. Storage means, and an activation decoder circuit for decoding the output of the activation storage means, the output of the activation decoder circuit is an activation signal, the test dedicated circuit, the test storage means, Rice plant And a test decoder circuit for decoding the output of the test storage means on condition that the test storage means is in a state of being able to be activated. The output of the test decoder circuit is used as a test signal, and the activation instruction voltage is applied to the activation terminal. Then, the input data of the activation storage means is outputted from the output side of the activation storage means, and when the activation instruction voltage is not applied to the activation terminal, the output data of the activation storage means is fixed and the test is performed. When the test instruction voltage is applied to the dedicated terminal and the activation instruction voltage is applied to the activation terminal, the input data of the test storage means is output from the output side of the test storage means, and the test instruction voltage is applied to the test dedicated terminal. When the test instruction voltage is not applied, the output data of the test storage means is fixed, and when the test instruction voltage is not applied to the dedicated test terminal, the test decoder circuit is enabled. And it is characterized in that a state.

[0012]

SUMMARY OF] illustrating the operation of the test mode setting circuit of the integrated circuit of the invention of claim 1. The test storage means is, for example,
D flip flop or D latch. for test
The storage means stores data from, for example, an address terminal of the integrated circuit.
Data A0... An are input. Test to test dedicated terminal
When the command voltage is applied, the data is stored in the test storage means.
Output from the output terminal. The output of the activation storage means is active.
Decoding by the activation decoder circuit and the activation decoder
Function block corresponding to each output of the circuit as an activation signal
And the output of the test storage means is a test decoder circuit.
And test each output of the test decoder circuit.
To the corresponding function block as a reset signal. The test mode setting circuit for an integrated circuit according to the first aspect of the present invention causes the same data to be input to the activation storage unit and the test storage unit,
The same data can be output from the activation storage unit and the test storage unit. Further, when the test instruction voltage is not applied to the dedicated test terminal, the output of the test storage means is decoded by the test decoder circuit, and each output of the test decoder circuit is sent to the corresponding functional block.

[0013] illustrating the operation of test mode setting circuit of the integrated circuit of the invention of claim 2. The test mode setting circuit for an integrated circuit according to claim 2 inputs the same data to the activation storage unit and the test storage unit when the test instruction voltage is applied to the test dedicated terminal. The same data is output from the activation storage unit and the test storage unit. Further, when the test instruction voltage is no longer applied to the test dedicated terminal, the output of the test storage means is decoded by the test decoder circuit, and each output of the test decoder circuit is sent to the corresponding functional block.

[0014]

FIG. 2 is a block diagram of a first embodiment of the present invention. In the figure, 1 indicates a latch, and 7 indicates an input buffer with a pull-up resistor. The latch 1 and the input buffer 7 exist in the integrated circuit. A signal from a test dedicated terminal TEST of the integrated circuit is input to an input buffer 7, and an output of the input buffer 7 is a gate terminal G of the latch 1.
Is input to When the signal applied to the test dedicated terminal TEST is at L level, L level is input to the input buffer 7. When nothing is connected to the test dedicated terminal TEST, or when the H level is applied, the H level is input to the input buffer 7 by the pull-up resistor.

The data input terminal of the latch 1 receives data from an address terminal of the integrated circuit. When the signal of the gate terminal G of the latch 1 is at L level (low level), the input data of the latch 1 is output as it is to the output terminals Q0.
n. The signal at the gate terminal G of the latch 1 is H
At the level, the output data at that time is maintained, and the output data does not change even if the input data changes. The output of the latch 1 becomes test A,..., Test n, and each test signal is sent to the corresponding function block.

The operation of FIG. 2 will be described. During normal operation, nothing is connected to the test dedicated terminal TEST, or H level is applied. Under this condition,
The output of the input buffer 7 with the pull-up resistor becomes H level, the H level is applied to the gate terminal G of the latch 1 of the test dedicated circuit, and the output Q0 of the latch 1 of the test dedicated terminal is applied.
... The signal of Qn is at L level. Immediately before the normal operation, the contents of the latch 1 are cleared.

In the test mode, the dedicated test terminal TE
L level is applied to ST. Test dedicated terminal TEST
When the L level is applied, the output of the input buffer 7 with the pull-up resistor goes to the L level, and the L level is applied to the gate terminal G of the latch 1 of the test dedicated circuit.
The values of the test mode selection signals A0 to An from the address terminals are set in the latch 1 of the test dedicated circuit. When the value of A0... An is set in the latch 1 of the test dedicated circuit, nothing is connected to the test dedicated terminal TEST to release the L level applied to the test dedicated terminal TEST, or H Apply level.

According to FIG . 2 , the test mode selection signal A
Various test modes can be set in accordance with the input values of 0... An, and it is not necessary to constantly apply the test mode signal to the test dedicated terminal TEST during the test mode. Further, by enabling the normal operation mode while maintaining the test mode, it is possible to select only the function to be tested and to test the integrated circuit without affecting other functions.

In the above description, the test-only terminal TEST
Is set to the test mode when an L level is applied thereto, but the test mode may be set when an H level is applied to the test dedicated terminal TEST.
In order to perform the test mode when the H level is applied to the test dedicated terminal TEST, the input buffer 7 with a pull-up function may be replaced with an input buffer having an inverter function with a pull-down resistor. In the above description, the data of the address terminal of the integrated circuit is input to the data input terminal of the latch 1. However, the data of the other input terminal of the integrated circuit is input to the data input terminal of the latch 1. Is also good.

FIG. 3 is a block diagram of a second embodiment of the present invention. In the figure, 1 is a latch, 2 is a decoder circuit,
Reference numeral 7 denotes an input buffer 7 with a pull-up resistor. The outputs Q0 to Qn of the latch 1 are input to the decoder circuit 2. The decoder circuit 2 has outputs of X0... Xm. However, m is 2n + 1 -1. If the outputs Q0... Qn of the latch 1 are all 0, for example, the decoder circuit 2
, Qn of the latch 1 are all 1, for example, only the output Xm of the decoder circuit 2 is turned on. The outputs X0... Xm of the decoder circuit 2 become the test A... Test m, and each test signal is sent to the corresponding functional block. Actually, the output X0 of the decoder circuit 2 is not used.

3 uses the test mode selection signals A0... An of n + 1 bits by inputting the value of the latch 1 of the test-only circuit to the decoder circuit 2 in addition to the effects of FIG. Thus, there is an effect that any one of the 2n + 1-1 test modes can be set.

FIG. 4 is a block diagram of a third embodiment of the present invention. In the figure, 1a is a latch for normal operation, 1b
Denotes a latch of a dedicated test circuit, 3 denotes an OR gate, and 7 denotes an input buffer with a pull-up resistor. Signals A0... An from the address terminals of the integrated circuit are applied to the data input terminals of the latch 1a for normal operation. The external terminal O of the integrated circuit is connected to the gate terminal GA of the latch 1a.
A signal from T is applied. Gate terminal G of latch 1a
When the signal A is at the L level, the signals A0 to An are output as they are, and when the signal at the gate terminal GA goes to the H level, the output at that time is maintained. Output N of latch 1a
The signals from Q0... NQn become signals A... Signal n, and each signal is sent to the corresponding functional block. For example, signal A
Is turned on, the corresponding functional block A enters an operating state (is activated).

The signals A0... An from the address terminals of the integrated circuit are applied to the data input terminals of the latch 1b of the test dedicated circuit.
Is applied, and each output of the latch 1b is sent to the corresponding function block as a test signal. OR gate 3 input C
A signal from the external terminal OT is applied to 1, and an output of the input buffer 7 is applied to an input C 2 of the OR gate 3.
The output of the OR gate 3 is applied to the gate terminal GB of the latch 1b of the dedicated test circuit.

The operation of FIG . 4 will be described. During a normal operation, the test dedicated terminal TEST is opened or an H level is applied. During normal operation, the output of the input buffer 7 with a pull-up resistor is at H level,
Since the H level is applied to the input C2 of the gate 3 and the H level is output from the output of the OR gate 3, the OR gate 3
Are not affected by the external terminal OT. An H level is applied to the gate terminal GB of the latch 1 which is a dedicated test circuit, and the outputs TQ0.
The signal of n becomes L level. Further, the values of the test mode selection signals A0... An from the address terminals are set in the normal operation latch 1a depending on the external terminal OT.

In the test mode, the dedicated test terminal T
L level is applied to EST. Test dedicated terminal TES
When the L level is applied to T, the output of the input buffer 7 with the pull-up resistor goes to the L level, and the L level is applied to the input C2 of the OR gate 3. OR gate 3 input C
When 2 is at the L level, the output of the OR gate 3 depends on the external terminal OT, so that the operation of the latch 1a for normal operation and the operation of the latch 1b of the dedicated test circuit are exactly the same.
When the external terminal OT goes low when the input C2 of the OR gate 3 is low, the low level is applied to the gate terminal GA of the latch 1a for normal operation, and at the same time, the gate of the latch 1b of the test-only circuit is opened. An L level is applied to the terminal GB, and the values of the signals A0 to An from the address terminals are set in the latches 1a and 1b.

A0... An are stored in the latch 1b of the dedicated test circuit.
Is set to release the L level applied to the test dedicated terminal TEST, the test dedicated terminal TEST is released.
Either nothing is connected to EST or H level is applied.

In the prior art, when a certain functional block in an integrated circuit is tested, the function block to be tested is set to operate in a normal operation, and then the test mode is switched to the test mode. It required two settings to test. In the third embodiment of the present invention, since the function block to be tested of the integrated circuit is set to the operating state and the function block to be tested can be tested at the same time, the function block to be tested is tested with one setting. I can do it.

FIG. 5 is a block diagram of a fourth embodiment of the present invention. In the figure, 1a is a latch for normal operation, 1b
Is a latch for a test-only circuit, 2a is a decoder circuit for normal operation, 2b is a decoder circuit for a test-only circuit, 3 is O
R gate 7 indicates an input buffer with a pull-up resistor. Output NQ0 of latch 1a for normal operation
.., NQn are sent to the decoder circuit 2a for normal operation. The decoder circuit 2a has outputs NX0 to NXm, and an output determined by the value of the input data is turned on.
Each of the outputs NX0 to NXm of the decoder circuit 2a is
It is sent to the corresponding function block.

Output TQ0 of Latch 1b of Test Only Circuit
.., TQn are sent to the decoder circuit 2b, which is a dedicated test circuit. The decoder circuit 2b has outputs TX0 to TXm, and an output determined by the value of the input data is turned on. Each of the outputs TX0 to TXm of the decoder circuit 2b is sent as a test signal to a test terminal of a corresponding functional block. Actually, the output NX0 of the decoder circuit 2a and the output TX0 of the decoder circuit 2b are not used.

The operation of FIG. 5 is similar to the operation of FIG.
Only the differences will be described. The outputs NQ0 to NQn of the latch 1a for normal operation are input to the decoder circuit 2a for normal operation, and the output TQ of the latch 1b of the test-only circuit is output.
Q0... TQn are input to a test-dedicated decoder circuit 2b, and outputs NX0.
m is generated and sent to each functional block, and the outputs TX0... TXm of the decoder circuit 2b of the test dedicated circuit are also generated and sent to the test terminals of each functional block. When the output NXi (i is 0, 1,..., M) of the decoder circuit 2a is on, the output TXi of the decoder circuit 2b is also on.

FIG . 5 shows a test mode selection signal A of n + 1 bits in addition to the effects of FIG.
By using 0... An, there is an effect that 2n + 1 -1 kinds of test modes can be obtained.

FIG. 6 is a block diagram of a fifth embodiment according to the first aspect of the present invention . In the figure, 1a is a latch for a normal operation, 1b is a latch for a test-only circuit, 2a is a decoder circuit for a normal operation, 2b is a decoder circuit for a test-only circuit, 5 is an inverter, 7 is an input buffer with a pull-up resistor. Are respectively shown.

Signals A0... From address terminals of the integrated circuit
An is applied to the data input terminal of the latch 1a for normal operation, and the signal from the external terminal OT of the integrated circuit is applied to the latch 1a.
Is applied to the gate terminal GA. Output NQ of latch 1a
.. NQn are applied to the data input terminals of the decoder circuit 2a for normal operation. The outputs NX0 of the decoder circuit 2a ...
Each of the NXm is sent to the corresponding function block.

The output of the input buffer 7 with pull-up is
The voltage is applied to the gate terminal GB of the latch 1 b of the test dedicated circuit and to the input of the inverter 5. The signals A0... An from the address terminals of the integrated circuit are applied to the data input terminals of the latch 1b. Output T of latch 1b
Q0... TQn are sent to the data input terminals of the decoder circuit 2b of the dedicated test circuit. The output of the inverter circuit 5 is applied to the gate terminal GC of the decoder circuit 2b.

The decoder circuit 2b has the gate terminal GC
When the level is applied, the enable state is established. Under the enable state, one of the plurality of output signal lines is turned on in accordance with the value of the input data TQ0 to TQn. When a high level is applied to the gate terminal GC, the decoder circuit 2b enters the non-enabled state. Under the non-enable state, the decoder circuit 2b outputs a predetermined value (for example, the output T
Only X0 is on and the other outputs TX1... TXm output all 0). TX0... TX of the decoder circuit 2b
Each of m is sent to the test terminal of the corresponding functional block. Note that the output N of the decoder circuit 2a is actually
X0 and the output TX0 of the decoder circuit 2b are not used.

The operation of the fifth embodiment will be described. During normal operation, nothing is connected to the test dedicated terminal TEST, or a high level is applied. During normal operation, the output of the input buffer 7 with the pull-up resistor is at the H level, and the H level is applied to the input terminal of the inverter circuit 5 and the gate terminal GB of the latch 1b. Thereby, the signals of the outputs TQ0 to TQn of the latch 1b become L level, and the L level is output to the output terminal of the inverter circuit 5, so that the output TX0 (test A) of the decoder circuit 2b is turned on. During normal operation, all 0s are stored in the latch 1b. Here, the address A0... An = 0... 0 is not used as a function inside the integrated circuit, and the output NX0 (signal A) of the decoder circuit 2a is an unused terminal.

In the test mode, the dedicated test terminal T
L level is applied to EST. Test dedicated terminal TES
When an L level is applied to T, the output of the input buffer 7 with a pull-up resistor goes to an L level, an L level is applied to the gate terminal GB of the latch 1b of the test dedicated circuit, and A0 from the address terminal is applied to the latch 1b. ... The value of An is set. Further, the external terminal OT is set to the L level at the same time when the test dedicated terminal TEST is set to the L level, and the same value as the value set in the latch 1b is set in the latch 1a.

Outputs NQ0... N of latches 1a for normal operation
The signal of Qn is input to the decoder circuit 2a for normal operation, and the outputs NX0 ... NX of the decoder circuit 2a for normal operation
After m is generated and sent to each functional block, the test dedicated terminal TEST is opened or the H level is applied to the test dedicated terminal TEST.

When the dedicated test terminal is opened or a high level is applied to the dedicated test terminal, the output of the inverter 5 goes low, and the decoder circuit 2b of the dedicated test circuit is enabled. When the decoder circuit 2b is enabled, the outputs TQ0.
Output TXi of decoder circuit 2b determined by the value of Qn
ON only, and the other outputs of the decoder circuit 2b are OFF. For example, when the output TX1 of the decoder circuit 2b is on, the output NX1 of the decoder circuit 2a is also on, so that the functional block B is activated and the data of the functional block B can be extracted to the outside of the integrated circuit. Become.

In the prior art, when a certain functional block of an integrated circuit is tested, it is necessary to activate the function block by a normal operation and then switch to a test mode to test the function block. Was needed. According to the fifth embodiment of the present invention, since the function block to be tested is activated and the function block to be tested can be tested at the same time, the function block to be tested can be tested with one setting. I can do it.

According to the fifth embodiment, the output TQ0... TQn of the test-only circuit latch 1b is used to obtain 2n + 1
-1 kinds of test modes can be obtained. Further, by enabling the normal operation mode while maintaining the test mode, it is possible to select only the function to be tested and to test the integrated circuit without affecting other functions.

FIG. 7 is a block diagram of a sixth embodiment according to the second aspect of the present invention . In the figure, 1a is a latch for a normal operation, 1b is a latch for a test-only circuit, 2a is a decoder circuit for a normal operation, 2b is a decoder circuit for a test-only circuit, 3 is an OR gate, 5 is an inverter, and 7 is a pull. The input buffer with an up resistor is shown.

Signals A0... From address terminals of the integrated circuit
An is applied to the data input terminal of the latch 1a for normal operation and to the data input terminal of the latch 1b of the test-only circuit. The signal from the external terminal OT of the integrated circuit is applied to the gate terminal GA of the latch 1a and to the input C1 of the OR gate 3. Latch 1a
NQ0 through NQn of the decoder circuits 2 for normal operation
a is sent to the data input terminal. Each of the outputs NX0 to NXm of the decoder circuit 2a is sent to a corresponding function block.

The output of the input buffer 7 with a pull-up resistor is applied to the input C2 of the OR gate 3 and also to the input of the inverter 5. The output of the OR gate 3 is applied to the gate terminal GB of the latch 1b of the dedicated test circuit. The output of the inverter 5 is applied to the gate terminal GC of the decoder circuit 2b of the test-only circuit.

The outputs TQ0... TQn of the latch 1b are sent to the data input terminal of the decoder circuit 2b. The decoder circuit 2b is enabled when an L level is applied to the gate terminal GC. Under the enabled state, the output circuits TX0... TXm corresponding to the values of the input data TQ0.
Is output. Each of the outputs TX0 to TXm of the decoder circuit 2b is sent to a test terminal of a corresponding functional block.

The operation of the sixth embodiment will be described. At the time of normal operation, the test dedicated terminal TEST is opened, or the H level is applied to the test dedicated terminal TEST. During normal operation, the output of the input buffer 7 with the pull-up resistor is at H level, H level is applied to the input C2 of the OR gate 3, the OR gate 3 outputs H level, and the output of the OR gate 3 is an external terminal. Not affected by OT. When the output of the OR gate 3 goes high, the high level is applied to the gate terminal GB of the latch 1b of the test-only circuit, and the signals of the outputs TQ0 to TQn of the latch 1b go low. Immediately before the normal operation, the latch 1b
Is cleared.

An external terminal O is connected to the latch 1a for normal operation.
Depending on T, the signal A0 from the address terminal of the integrated circuit
... An is set. During normal operation, the H level is applied to the input terminal of the inverter 5, and the output of the inverter 5 goes to the L level. When the inverter 5 outputs the L level, the decoder circuit 2b of the test-only circuit is enabled, and the decoder circuit 2b turns on only the output TX0 corresponding to the input data (all 0s) at the time. Here, the addresses A0... An = 0... 0 are not used as functions inside the integrated circuit, and the output NX0 of the decoder circuit 2a for normal operation is an unused terminal.

In the test mode, the dedicated test terminal T
L level is applied to EST. Test dedicated terminal TES
When the L level is applied to T, the L level is output from the input buffer 7 with the pull-up resistor, and the L level is applied to the input C2 of the OR gate 3 to cause the OR gate 3
Is dependent on the external terminal OT, the operation of the latch 1a for normal operation and the operation of the test-only circuit 1b are exactly the same.

When the external terminal OT goes low when the output of the input buffer 7 is low, the gate terminal GA of the latch 1a for normal operation and the latch 1
The L level is applied to the gate terminal GB of b. When the L level is applied to the gate terminal GA and the gate terminal GB, the values of the signals A0... An from the address terminals are set in the latches 1a and 1b, and the outputs NQ0.
n is input to the decoder circuit 2a, the output TQ0... TQn signal of the latch 1b is input to the decoder circuit 2b, and the output NX of the normal operation decoder circuit 2a is output.
NXm are generated and sent to each functional block. After sending a signal for activation to each functional block, an H level is applied to the test dedicated terminal TEST or nothing is connected.

When the H level is applied to the test dedicated terminal TEST or nothing is connected, the output of the inverter 5 becomes L level, and the L level is applied to the gate terminal GC of the decoder circuit 2b of the test dedicated circuit. , TQn of the latch 1b of the dedicated test circuit are input to the decoder circuit 2b, and the outputs TX0... TXm of the decoder circuit 2b are generated, and the same functional blocks as the outputs NX0. Is applied to the test terminal of

In the prior art, when a function block of an integrated circuit is to be tested, the function block to be tested is operated by normal operation, and then the state of the function block to be tested is made visible from the outside. Although two settings are required, according to the sixth embodiment of the present invention, the function block to be tested can be tested with one setting. Further, 2n + 1-1 types of test modes can be obtained by using the outputs TQ0 to TQn of the latch 1b of the dedicated test circuit. Furthermore, by enabling the normal operation mode while maintaining the test mode, it is possible to select only the function to be tested and test the integrated circuit without affecting other functions.

FIG. 8 shows a latch composed of D flip-flops. Latches 1, 1 used in FIGS.
a and 1b are external input terminals of the integrated circuit (for example,
Any circuit may be used as long as it can store the values of the signals A0 to An from the address terminals). For example, FIG. 8 shows a circuit configuration when the latches 1, 1a, and 1b are configured by D flip-flops. The D flip-flop in FIG. 8 outputs input data A0 to An when the signal TEST falls, and holds the output data until the next falling. The system reset signal shown in FIG. 8 is obtained from an external input terminal.

[0053]

As is apparent from the above description, according to the present invention, it is possible to (a) easily switch between a plurality of test modes of an integrated circuit. (b) Since the size of the package can be reduced, high-density mounting becomes possible, and the price is reduced. (c) There is no need to constantly input the test mode signal to the dedicated test terminal. Therefore, when the circuit other than the function to be tested is directly connected to the same dedicated test terminal, the function test can be performed without affecting the circuit other than the function to be tested. (d) Since the same address as the address indicating the functional block to be activated is latched in the dedicated test circuit, the functional block can be tested with a single setting, and the normal operation mode is maintained while maintaining the test mode. By enabling the function, it is possible to selectively test only the function to be tested without affecting other functions. (e) Even if the integrated circuit is complicated, it is possible to test for each block and each function, and as the number of test patterns decreases,
Product testing time can also be significantly reduced. And other remarkable effects.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a first embodiment of the present invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a block diagram of a third embodiment of the present invention.

FIG. 5 is a block diagram of a fourth embodiment of the present invention.

FIG. 6 is a block diagram of a fifth embodiment of the present invention.

FIG. 7 is a block diagram of a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a latch constituted by D flip-flops.

FIG. 9 is a diagram illustrating a configuration example of an integrated circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Latch of dedicated test circuit 1a Latch for normal operation 1b Latch of dedicated test circuit 2 Decoder circuit of dedicated test circuit 2a Decoder circuit for normal operation 2b Decoder circuit of dedicated test circuit 3 OR gate 5 Inverter 7 Input with pull-up resistor buffer

Continuation of the front page (56) References JP-A-1-54380 (JP, A) JP-A-3-296675 (JP, A) JP-A-59-160778 (JP, A) JP-A-6-201794 (JP) JP-A-2-124483 (JP, A) JP-A-4-181186 (JP, A) JP-A-6-3424 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB G01R 31/28-31/3185 H01L 21/66 H01L 21/822

Claims (2)

(57) [Claims] 1. A test dedicated terminal, one activation terminal, an external output terminal, a plurality of functional blocks, a test dedicated circuit for outputting a plurality of test signals, and a plurality of activation signals An activation circuit that outputs the data of the functional block associated with the test signal from the external output terminal when the test signal is on, and outputs the data to the activation signal when the activation signal is on. A test mode setting circuit for an integrated circuit in which an associated function block is activated, the activation circuit comprising: an activation storage unit; and an activation unit for decoding an output of the activation storage unit. A decoding circuit for
The output of the activation decoder circuit is used as an activation signal, and the test-only circuit has a test storage circuit and a test decoder circuit for decoding the output of the test storage device on condition that the test storage circuit is enabled. The output of the test decoder circuit is used as a test signal, and when an activation instruction voltage is applied to the activation terminal, the input data of the activation storage means is output from the output side of the activation storage means. When the activation instruction voltage is not applied to the test terminal, the output data of the activation storage means is fixed, and when the test instruction voltage is applied to the test dedicated terminal, the input data of the test storage means is output from the test storage means. When the test instruction voltage is not applied to the dedicated test terminal, the output data of the test storage means is fixed, and the test instruction voltage is applied to the dedicated test terminal. A test mode setting circuit for an integrated circuit, wherein a test decoder circuit is enabled when not applied. 2. A dedicated test terminal, a single activation terminal, an external output terminal, a plurality of function blocks, a dedicated test circuit for outputting a plurality of test signals, and a plurality of activation signals An activation circuit that outputs the data of the functional block associated with the test signal from the external output terminal when the test signal is on, and outputs the data to the activation signal when the activation signal is on. A test mode setting circuit for an integrated circuit in which an associated function block is activated, the activation circuit comprising: an activation storage unit; and an activation unit for decoding an output of the activation storage unit. A decoding circuit for
The output of the activating decoder circuit is used as an activating signal, and the dedicated test circuit has a test storing means and a test decoder circuit for decoding the output of the test storing means on condition that it is in an enabled state. The output of the test decoder circuit is used as a test signal, and when an activation instruction voltage is applied to the activation terminal, the input data of the activation storage means is output from the output side of the activation storage means. When the activation instruction voltage is not applied to the test terminal, the output data of the activation storage means is fixed, and when the test instruction voltage is applied to the test dedicated terminal and the activation instruction voltage is applied to the activation terminal, the test is performed. When the test instruction voltage is not applied to the test dedicated terminal, the output data of the test storage means is output from the output side of the test storage means. A test mode setting circuit for an integrated circuit, wherein the test decoder circuit is enabled when a test instruction voltage is not applied to a dedicated test terminal.