JPS6145898B2 - - Google Patents

Abstract

PURPOSE:To facilitate check by making it possible to write an arbitrary signal to the FF group and read the output signal arbitrarily in the logical integrated circuit incorporating a programmable logic array equipped with FFs. CONSTITUTION:When control signal ''0'' is applied to control signal line 402 of power source voltage supply control means 4, diodes 451-45N become conductive to make respective product terms lines 1031-103N zero-potential, and diodes 461-46N are nonconductive, and the power source voltage is supplied to the first and second buses 5011-501N and 5021-502N, and AND array 1 is unoperatable logically. At this time, the external input signal is transferred to input signal lines 2021-202N of the FF group through signal lines 1011-101N, diodes 511-51N, the first buses 5011-501N and diodes 531-53N and is written to FF group 3. The output signal of FF group 3 is tranferred to external signal lines 2011-201N through diodes 521-52N, the second buses 5021-502N and diodes 541- 54N and is read.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to testable logic integrated circuits, and more particularly to logic integrated circuits that make programmable logic arrays with flip-flops testable.

Programmable logic arrays (hereinafter referred to as PLA) are rapidly becoming popular as general-purpose logic integrated circuit elements with a regular structure due to their wide range of uses and ease of design, but they are also becoming more popular in terms of fault testing. It is required to be simple, and it is especially important that failure testing of the logic array portion arbitrarily programmed by the user can be carried out with simple effort and low cost.

PLA has more complex structures that can incorporate flip-flops to create sequential circuits.
However, such highly integrated PLA has limitations such as a limited number of input/output terminals and the inability to directly refer to the internal structure, and it takes a huge amount of time and effort to inspect complex sequential circuit functions. In reality, failure inspection of PLA has become extremely difficult.

For this reason, in highly integrated PLA, circuit configurations may be devised in advance to facilitate failure testing. traditionally known
The method for configuring PLA circuits that are easy to test involves configuring multiple built-in flip-flops so that they operate as shift registers during testing, making it possible to directly input and output test information to these flip-flops. There is a so-called scan path method. This scan pass method has the great advantage that testing can be easily carried out by treating sequential circuits as combinational circuits, and is also characterized in that it can be realized with the addition of fewer input/output terminals.

However, with this scan pass method, test information is written and read by shifting in and out each time each test input is applied, which is a serious problem in that it wastes time during the test and impedes the high speed of the test. There are some drawbacks.

Another drawback is that the structure for switching the configuration of the flip-flop group becomes complicated.

SUMMARY OF THE INVENTION In view of these drawbacks, it is an object of the present invention to provide an easy-to-test logic integrated circuit that has a simple circuit configuration, allows easy testing, and can be performed at high speed.

According to the present invention, the circuit comprises a programmable AND array, a programmable OR array, and a group of flip-flops, and a part of the output signal of the OR array is passed through the flip-flops to the AND array. A logic integrated circuit configured to feed back a part of an input signal, comprising a first bus group and a second bus group, and wherein the first bus group or the second bus group or the AND array means for selectively supplying a power supply voltage to either one of the product term line groups; and a signal from a signal line for transmitting an external input signal among the input signal line groups of the AND array to the first bus line group. a first switch group for controlling transmission; and a second switch group for controlling signal transmission from signal lines transmitting output signals of the flip-flop group to the second bus group among the input signal line groups of the AND array. a third group of switches for controlling signal transmission from the first bus group to signal lines for transmitting the input signals of the flip-flop group among the output signal lines of the OR array; and the second bus group. a fourth switch group for controlling signal transmission to signal lines transmitting external output signals among the output signal line groups of the OR array; When a power supply voltage is supplied to the line group, the first, second, third and fourth switch groups electrically disconnect the first and second bus groups from the AND array and the OR array, A normal logic operation programmed in the AND array and the OR array is enabled, and a power supply voltage selected by the power supply voltage supplying means is supplied to the first and second busbar groups. At this time, the input signal from the outside is transmitted to the first bus group through the first switch group, and further supplied as the input signal to the flip-flop group through the third switch group, and the output signal of the flip-flop group is transmitted to the second bus group. are transmitted to the second bus group through the switch group, and further derived as an output signal to the outside through the fourth switch group. An easy-to-test logic integrated circuit is obtained that allows parallel signals to be read out at the same time.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1 is a logical product (hereinafter referred to as AND) array, which is composed of a programmable diode matrix. 2 is a logical sum (hereinafter referred to as OR)
The array consists of a diode matrix that is also programmable. a, a', etc. represent the intersection points of the diode matrix,
Details are shown in Figure 2. In the figure, 13 is a diode, and 14 is a fuse. By cutting the fuse 14, it is possible to program the program as desired. Referring again to FIG. 1, 3 is a D-type master-slave flip-flop group;
Configure an N-bit register. In order to simplify the explanation, as an example, both the external input signal and the external output signal are assumed to be N bits. A signal line 301 supplies a synchronizing signal line for driving the flip-flop group 3. A signal line 302 supplies an initialization signal for setting the flip-flop group 3 to a predetermined initial state. 101,...,101
_N is an external input signal line and also an AND array 1
This is part of the input signal line. 102 ₁ ,...,10
2 _N is the output signal line of the flip-flop group 3 and is also another input signal line of the AND array 1. 11 ₁ ,..., 11 _N , 12 ₁ ,..., 12 _N are logic inversion (hereinafter referred to as NOT) circuits, and input signal lines 101 ₁ ,..., 101 _N , 1 of the AND array 1
The signals on 02 ₁ , . . . , 102 _N are inverted and applied to yet another input signal line of AND array 1. 10
3 ₁ , 103 ₂ , . . . , 103 _N are output signal lines of the AND array 1 and transmit the result of the AND operation to the OR array 2. That is, 103 ₁ , 103 ₂ ,
..., 103 _N is the product term line. 401 is a power line to which a positive voltage is supplied from the outside. 41 ₁ ,
41 ₂ ,...,42 _N are resistors, and each product term line 1
03 ₁ , 103 ₂ , . . . , 103 _N are supplied with power supply voltage through these resistors. 201,...,
_201N is an external output signal line and is also a part of the output signal line of the OR array 2. 202 ₁ ,…,
202 _N is an input signal line of the flip-flop group 3 and another output signal line of the OR array 2. 21 ₁ ,..., 21 _N , 22 ₁ ,..., 22 _N are resistors, and the output signal lines 201 ₁ ,..., 201 _N , 202 ₁ ,..., of the OR array 2 are connected via these resistors.
202 _N is connected to the ground line 203. The configuration of a typical PLA has been explained above.

Next, the configuration of a circuit added to facilitate inspection will be explained. 501 ₁ , . . . , 501 _N are first bus bars, and 502 ₁ , _.

51 ₁ ,..., 51 _N are diodes, and the external input signal lines 101 ₁ ,..., 101 _N are connected to the corresponding first bus lines 501 ₁ ,..., 5, respectively.
01 Connected to _N. That is, 51 ₁ ,...,51 _N
is the first switch group that controls the input of the first bus. 52 ₁ ,..., 52 _N are diodes, and output signal group 102 of flip-flop group 3
₁ , . . . , 102 _N are connected to corresponding second busbars 502 ₁ , . . . , 502 _N via these. That is, 52 ₁ , . . . , 52 _N is a second switch group that controls the input of the second bus. 53
₁ ,..., _53N are diodes, and input signal lines ₂₀₂₁ ,..., _202N of flip-flop group 3
are connected to the corresponding first busbars 5 through these
01 ₁ , ..., 501 ₂ . i.e. 5
3 ₁ , . . . , 53 _N is a third switch group that controls the output of the first bus. 54 ₁ ,..., 54 _N are diodes, and external output signal lines 201,...,
201 _N is connected to the corresponding second
are connected to the busbars 502,..., 502N _of . That is, 54 ₁ , . . . , 54 _N is a fourth switch group that controls the output of the second bus. Reference numeral 4 denotes means for controlling the supply of power supply voltage, and is provided for selectively supplying power supply voltage to either the product term line group or the first and second bus line groups. A control signal line 402 is applied with a control signal for selecting a group of signal lines to which a power supply voltage is to be supplied. 44 is
A NOT circuit inverts the control signal and outputs it.
45 ₁ , 45 ₂ , . . . , 45 _N are diodes which become conductive when the control signal “0” is applied to the control signal line 402 and cause the respective product term lines 103 ₁ , 103
₂ ,...,103 _N is set to "0" and the supply of power supply voltage is cut off. 46 ₁ ,..., 46 _N and 47 ₁ ,
..., 47 _N is a diode, and the control signal line 40
When control signal line "1" is applied to 2, that is, when "0" is output to NOT circuit 44, conduction occurs, and the respective first bus lines 501 ₁ , . . . , 501
The potentials of _N and the second bus lines 502 ₁ , . . . , 502 _N are set to “0” and the supply of power supply voltage is cut off. That is,
Depending on the control signal applied to the control signal line 402, the product term lines 103 ₁ ,..., 103 _N or the first and second bus lines 501 ₁ ,..., 501 _N , 502 ₁ ,...,
_502N can be selected and supplied with the power supply voltage.

When the product term lines 103 ₁ ,..., 103 _N receive power supply voltage, the first and second bus lines 501 ₁ ,
Since the potential of ..., 501 _N , 502 ₁ , ..., 502 _N is "0", all the diodes 51 ₁ , ..., 54 _N of the first, second, third, and fourth switch groups
becomes non-conductive, and the first and second busbars become AND
Does not affect array 1 and OR array 2. At this time, normal logic operations programmed in AND array 1 and OR array 2 become possible.

In addition, the first and second bus lines 501 ₁ ,..., 501
When _N , 502 ₁ ,..., 502 _N is supplied with the power supply voltage, the product term lines 103 ₁ , 103 ₂ ,..., 10
Since the potential of _3N is "0", the normal logic operation programmed into AND array 1 is disabled and its output does not affect OR array 2. Furthermore, in this state, the external input signal lines 101 ₁ ,
..., 101 _N , the diodes 51 ₁ , ..., of the first switch group are applied.
51 _N through the first bus bar 501 ₁ ,...,501 _N
Then, the diode 53 of the third switch group
The external input signal is transmitted to the input signal lines 202 ₁ , . . . _, 202 _N of the flip-flop group through the input signal lines 202 1 _, . Also, the output signal of flip-flop group 3 is
through the diodes 52 ₁ ,..., 52 _N of the switch group to the second bus bar 502 ₁ ,..., 502 _N , and further to the diodes 54 ₁ ,..., 5 of the fourth switch group.
4 _N through external output signal lines 201 ₁ ,..., 201 _N
and can be read externally.

The above explains the normal logic operation of the PLA and the ability to input and output parallel signals from the built-in flip-flop group.

Next, another embodiment of the present invention will be shown.

FIG. 3 is a circuit diagram showing an embodiment in which the built-in flip-flop is of the JK type as an example of one that is controlled by two inputs. Only necessary parts are shown in the figure, and the same reference numerals as in FIG. 1 indicate the same components. 3' is JK
It is a type master-slave flip-flop, and in order to write any value to it, two inputs, J and K, are required.
It is sufficient to apply mutually inverted signals to the two inputs.
51 ₁ ′, 52 ₁ ′, and 46 ₁ ′ are diodes, 501 ₁ ′ is the first bus bar, and 202 ₁ ′ is the flip-flop group 3 ′.
These configurations are additionally added to the embodiment shown in FIG. 1, and the operations of each part are the same. Diode 51 ₁ ' is NOT circuit 1
₁ receives the output signal of bus 501 ₁ and 5.
01 ₁ ' are transmitted with mutually inverted signals, and furthermore, mutually inverted signals are applied to two inputs of the flip-flop group 3' through input signal lines 202 ₁ and 202 ₁ '.

FIG. 4 is a circuit diagram showing another embodiment of the means 4 for controlling the supply of power supply voltage shown in FIG. 48,
Reference numeral 49 denotes a transistor, one of which is controlled to be conductive by a control signal applied to the control signal line 402. 403 is a power line for the product term line, and 404 is a power line for the bus bar. A power supply voltage supplied through a power supply line 401 connected to an external terminal is connected to a transistor 48 on one side.
to each product term line 103 ₁ ,..., 103 _N via a transistor 49 to each of the first and second bus lines 501 ₁ ,..., 501 _N , 502 ₁ ,..., 50
_2N , and only to one of the signal line groups.

Note that in this embodiment, the power supply voltage 4 to the product term line
03 and the power supply lines 404 to the first and second busbars may be connected to separate external terminals so that either one of them is directly supplied with a power supply voltage from the outside. That is, transistors 48, 4
9. The switch means consisting of the NOT circuit 44 does not necessarily need to be provided in the present logic integrated circuit, and the same purpose can be achieved if it is provided, for example, as a function of an external inspection device. be.

FIG. 5 is a circuit diagram showing another embodiment of the first or second switch group, in which only the portion corresponding to the diode 511 in FIG _{. 1} is shown. 51
₁ ″ is a transistor, and external input signal line 101
₁ signal is inverted and transmitted to the first bus ₅₀₁₁ . Therefore, in this case, the signal input from the outside is inverted and written to the flip-flop, and the output signal of the flip-flop group is inverted and read out to the outside, but there is no problem in using it for the purpose of testing the circuit. Must not be.

In the above description, it has been assumed that the external input/output signal and the built-in flip-flop group have the same number of bits, but it is easily inferred that the above embodiment can be applied even if the number of the former is greater than the latter.

To summarize the above explanation, by being able to write any signal to the flip-flop group built into the PLA and read out the output signal at will,
Tests can be easily performed by treating complex sequential circuits as combinational circuits, and tests can be performed at high speed because the writing and reading can be performed in parallel and at the same time. According to the present invention, the output lines of the OR array are effectively used, the objective is achieved by providing a relatively simple additional circuit and a small number of additional control terminals, and furthermore, the inspection cost is reduced by combining these. This is the effect of

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure shows the details of the intersection point of the diode matrix, Figure 3 is a circuit diagram of the main part showing an embodiment in which the built-in flip-flop group is JK type, and Figure 4 is the means for controlling the supply of power supply voltage. FIG. 5 is a diagram showing the main parts of another embodiment of the first or second switch group. In the figure, 1...AND array, 2...OR array, 3...D-type flip-flop group, 3'...JK-type flip-flop, 4...means for controlling supply of power supply voltage, 51 ₁ ,..., 51 _N , 51 ₁ '... Diodes forming the first switch group, 52 ₁ ,..., 52
_N , 52 ₁ ′...Diode forming the second switch group, 53 ₁ ,..., 53 _N ... Diode forming the third switch group, 54 ₁ ,..., 54 _N ... Fourth
Diodes 11 ₁ , which constitute the switch group of
...,11 _N ,12 ₁ ,...,12 _N ,44...NOT circuit, 13,45 ₁ ,...,45 _N ,46 ₁ ,...,4
6 _N , 47 ₁ ,..., 47 _N , 46 ₁ '...diode,
14... Fuse, 48, 49, 51 ₁ ″... Transistor, 21 ₁ ,..., 21 _N , 22 ₁ ,..., 22 _N ,
41 ₁ ,...,41 _N ,42 ₁ ,...,42 _N ,43
₁ ,...,43 _N ...resistor, a, a'...crossing point of diode matrix.

Claims (1)

[Claims] 1 consists of a programmable AND array, a programmable OR array, and a group of flip-flops, and a part of the output signal of the OR array is passed through the flip-flop group to a part of the input signal of the AND array. A logic integrated circuit configured to feed back to means for selectively supplying a power supply voltage to one of the input signal lines, and a signal from some or all of the signal lines of the input signal line group of the AND array for transmitting input signals from the outside to the first bus group. a first switch group for controlling the transmission; and a second switch group for controlling the signal line transmission from the signal line transmitting the output signal of the flip-flop group among the input signal line group of the AND array to the second bus group. a third switch group for controlling signal transmission from the first bus group to a signal line transmitting the input signal of the flip-flop group among the output signal line group of the OR array;
a fourth switch group for controlling signal transmission from the bus group to some or all of the signal lines transmitting output signals to the outside among the output signal line group of the OR array; When the power supply voltage is selected by the means for supplying the product term line group and the power supply voltage is supplied to the product term line group, the first, second, third and fourth switch groups select the first and second bus line groups from the logic line group. electrically disconnected from the product array and the OR array to enable normal logic operations programmed in the AND array and the OR array; , when the power supply voltage is supplied to the second bus group, the input signal from the outside is transmitted to the first bus group through the first switch group, and is further transmitted as an input signal to the flip-flop group through the third switch group. and the output signal of the flip-flop group is transmitted to a second bus group through a second switch group, and further led out as an output signal to the outside through a fourth switch group.
An easily testable logic integrated circuit that allows parallel signals to be written to the flip-flop group and parallel signals to be read from the flip-flop group at the same time.