JPS5679321A - Reporting system for operation state - Google Patents

Reporting system for operation state

Info

Publication number
JPS5679321A
JPS5679321A JP15601079A JP15601079A JPS5679321A JP S5679321 A JPS5679321 A JP S5679321A JP 15601079 A JP15601079 A JP 15601079A JP 15601079 A JP15601079 A JP 15601079A JP S5679321 A JPS5679321 A JP S5679321A
Authority
JP
Japan
Prior art keywords
controller
channel
operation state
bus
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15601079A
Other languages
Japanese (ja)
Inventor
Hajime Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15601079A priority Critical patent/JPS5679321A/en
Publication of JPS5679321A publication Critical patent/JPS5679321A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To know the operation state of an I/0 controller by performing a select sequence by permitting the I/O controller to inform a channel of it operation state by making use of the period when the I/O controller is not coupled with the channel.
CONSTITUTION: Bus line 3 connected to the channel and operational in line 4 are connected to more than one I/O controller to constitute an input-output system. Cable driver 5 and cable receiver 6 of this controller are connected to in line 4, and bus in bits 0W7 of bus line 3 to bus drivers 7-0W7-7 respectively. Further, AND circuits 9-0W9-7 receiving operational in information on their system and AND circuits 10-0W10-7 with NOT input are connected to drivers 7-0W7-7. If all I/O controller including those of this system are not coupled with the channel, the output of receiver 6 is held at zero and the output of address recorder 11 is supplied to drivers 7-0W7-7 by way of circuits 10-0W10-7, so that the operation state can be reported to the channel.
COPYRIGHT: (C)1981,JPO&Japio
JP15601079A 1979-11-30 1979-11-30 Reporting system for operation state Pending JPS5679321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15601079A JPS5679321A (en) 1979-11-30 1979-11-30 Reporting system for operation state

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15601079A JPS5679321A (en) 1979-11-30 1979-11-30 Reporting system for operation state

Publications (1)

Publication Number Publication Date
JPS5679321A true JPS5679321A (en) 1981-06-29

Family

ID=15618345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15601079A Pending JPS5679321A (en) 1979-11-30 1979-11-30 Reporting system for operation state

Country Status (1)

Country Link
JP (1) JPS5679321A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05233479A (en) * 1992-02-19 1993-09-10 Nec Corp Panel monitor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05233479A (en) * 1992-02-19 1993-09-10 Nec Corp Panel monitor system

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