JPS54162457A - Electrode forming method for semiconductor element - Google Patents

Electrode forming method for semiconductor element

Info

Publication number
JPS54162457A
JPS54162457A JP7088878A JP7088878A JPS54162457A JP S54162457 A JPS54162457 A JP S54162457A JP 7088878 A JP7088878 A JP 7088878A JP 7088878 A JP7088878 A JP 7088878A JP S54162457 A JPS54162457 A JP S54162457A
Authority
JP
Japan
Prior art keywords
electrode
evaporated
bonding
semiconductor element
forming method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7088878A
Other languages
English (en)
Inventor
Hirohisa Abe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7088878A priority Critical patent/JPS54162457A/ja
Publication of JPS54162457A publication Critical patent/JPS54162457A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12036—PN diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
JP7088878A 1978-06-14 1978-06-14 Electrode forming method for semiconductor element Pending JPS54162457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7088878A JPS54162457A (en) 1978-06-14 1978-06-14 Electrode forming method for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7088878A JPS54162457A (en) 1978-06-14 1978-06-14 Electrode forming method for semiconductor element

Publications (1)

Publication Number Publication Date
JPS54162457A true JPS54162457A (en) 1979-12-24

Family

ID=13444508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7088878A Pending JPS54162457A (en) 1978-06-14 1978-06-14 Electrode forming method for semiconductor element

Country Status (1)

Country Link
JP (1) JPS54162457A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180430A (ja) * 1985-02-06 1986-08-13 Toshiba Corp 半導体装置の電極形成方法
JPS63204620A (ja) * 1987-02-11 1988-08-24 バウマー　エレクトリク　アクチエンゲゼルシャフト ハイブリッド厚膜回路におけるボンデイングワイヤとコンタクト領域との間の接続形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61180430A (ja) * 1985-02-06 1986-08-13 Toshiba Corp 半導体装置の電極形成方法
JPS63204620A (ja) * 1987-02-11 1988-08-24 バウマー　エレクトリク　アクチエンゲゼルシャフト ハイブリッド厚膜回路におけるボンデイングワイヤとコンタクト領域との間の接続形成方法

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