JPS54161891A - Field effect transistor - Google Patents

Field effect transistor

Info

Publication number
JPS54161891A
JPS54161891A JP7113578A JP7113578A JPS54161891A JP S54161891 A JPS54161891 A JP S54161891A JP 7113578 A JP7113578 A JP 7113578A JP 7113578 A JP7113578 A JP 7113578A JP S54161891 A JPS54161891 A JP S54161891A
Authority
JP
Japan
Prior art keywords
region
electrode
gate
type
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7113578A
Other languages
Japanese (ja)
Inventor
Sukemitsu Takena
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7113578A priority Critical patent/JPS54161891A/en
Publication of JPS54161891A publication Critical patent/JPS54161891A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure an assured gate function as well as to increase the dielectric strength by forming the drain region constituting the J-FET within the semiconductor substrate more deeply than the gate region and thus suppressing the air depletion layer extending into the drain region.
CONSTITUTION: P+-type region 7 is formed by diffusion on the back of P-type semiconductor substrate 6 to be used as the gate region with attachment of gate electrode G2. And N+-type source and drain regions 9 and 10 going deep into substrate 6 are formed by diffusion on the surface of the substrate with attachment of source electrode S and drain electrode D each. Then shallow N-type region 8 is formed by diffusion on the surface of substrate 6 excluding region 9 and 10, and furthermore shallower P+-type gate region 11 is provided within region 8 between region 9 and 10 with attachment of gate electrode G1. In such constitution, electrode S is earthed with electrode D applied with the positive voltage along with electrode G1 and G2 applied with the negative voltage respectively. As a result, the gate function becomes assured near the surface of the N+N junction due to the effect in that the depletion layer does not extend into region 10 air particularly.
COPYRIGHT: (C)1979,JPO&Japio
JP7113578A 1978-06-12 1978-06-12 Field effect transistor Pending JPS54161891A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7113578A JPS54161891A (en) 1978-06-12 1978-06-12 Field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7113578A JPS54161891A (en) 1978-06-12 1978-06-12 Field effect transistor

Publications (1)

Publication Number Publication Date
JPS54161891A true JPS54161891A (en) 1979-12-21

Family

ID=13451824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7113578A Pending JPS54161891A (en) 1978-06-12 1978-06-12 Field effect transistor

Country Status (1)

Country Link
JP (1) JPS54161891A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340739A (en) * 2004-05-31 2005-12-08 Matsushita Electric Ind Co Ltd Switching circuit and semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005340739A (en) * 2004-05-31 2005-12-08 Matsushita Electric Ind Co Ltd Switching circuit and semiconductor device
JP4559772B2 (en) * 2004-05-31 2010-10-13 パナソニック株式会社 Switch circuit

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