JPS54153574A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54153574A
JPS54153574A JP6250578A JP6250578A JPS54153574A JP S54153574 A JPS54153574 A JP S54153574A JP 6250578 A JP6250578 A JP 6250578A JP 6250578 A JP6250578 A JP 6250578A JP S54153574 A JPS54153574 A JP S54153574A
Authority
JP
Japan
Prior art keywords
layer
film
opening
metal
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6250578A
Other languages
Japanese (ja)
Inventor
Shigeru Komatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6250578A priority Critical patent/JPS54153574A/en
Publication of JPS54153574A publication Critical patent/JPS54153574A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To establish the semiconductor device high in reliability and without any hindrance to the increase in layered metal.
CONSTITUTION: The first metal layer 13a is formed on the insulation layer 15 (Fig. 4A), the thermoplastic fluorine resin layer 16 is formed so that a part of the layer 13a and the insulation layer 15 are covered, and the fluorine resin is partly molten to make complete the bonding of the ground layers 13a and 15. (Fig. 4B) The opening 17 is provided in the layer 16 by taking the photo resist film 18 as a mask, the surface of a part of the layer 13a is exposed, (Fig. 4C), and after completely removing the film 18, the second metal layer is formed by using electric plating. (Fig. 4D) To form the second metal layer, the metal film 20 is formed entirely on the fluorine resin 16 and the metal layer 13a exposed in the opening 17 (Fig. 4E) and the photo resist film 21 is formed on the film 20, and the opening 22 corresponding to the opening 17 is formed. (Fig. 4F) Further, the increased layer 19 is formed by taking the film 20 as an electrode with electric plating through the coating of gold, and the semiconductor device (Fig. 3) is established, by removing the film 21 and the film 20 not covered with the gold layer 19.
COPYRIGHT: (C)1979,JPO&Japio
JP6250578A 1978-05-25 1978-05-25 Manufacture for semiconductor device Pending JPS54153574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6250578A JPS54153574A (en) 1978-05-25 1978-05-25 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6250578A JPS54153574A (en) 1978-05-25 1978-05-25 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54153574A true JPS54153574A (en) 1979-12-03

Family

ID=13202089

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6250578A Pending JPS54153574A (en) 1978-05-25 1978-05-25 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54153574A (en)

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