JPS54153563A - Logical array circuit - Google Patents

Logical array circuit

Info

Publication number
JPS54153563A
JPS54153563A JP6267178A JP6267178A JPS54153563A JP S54153563 A JPS54153563 A JP S54153563A JP 6267178 A JP6267178 A JP 6267178A JP 6267178 A JP6267178 A JP 6267178A JP S54153563 A JPS54153563 A JP S54153563A
Authority
JP
Japan
Prior art keywords
lines
output
input
array
internal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6267178A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6323685B2 (US20030199744A1-20031023-C00003.png
Inventor
Hiroshi Mayumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6267178A priority Critical patent/JPS54153563A/ja
Priority to DE19792921363 priority patent/DE2921363A1/de
Publication of JPS54153563A publication Critical patent/JPS54153563A/ja
Priority to US06/331,744 priority patent/US4431926A/en
Publication of JPS6323685B2 publication Critical patent/JPS6323685B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
    • H03K5/15066—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages using bistable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/78—Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1502—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs programmable

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
JP6267178A 1978-05-24 1978-05-24 Logical array circuit Granted JPS54153563A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6267178A JPS54153563A (en) 1978-05-24 1978-05-24 Logical array circuit
DE19792921363 DE2921363A1 (de) 1978-05-24 1979-05-25 Signalgenerator
US06/331,744 US4431926A (en) 1978-05-24 1981-12-17 Counter controlled signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6267178A JPS54153563A (en) 1978-05-24 1978-05-24 Logical array circuit

Publications (2)

Publication Number Publication Date
JPS54153563A true JPS54153563A (en) 1979-12-03
JPS6323685B2 JPS6323685B2 (US20030199744A1-20031023-C00003.png) 1988-05-17

Family

ID=13206980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6267178A Granted JPS54153563A (en) 1978-05-24 1978-05-24 Logical array circuit

Country Status (3)

Country Link
US (1) US4431926A (US20030199744A1-20031023-C00003.png)
JP (1) JPS54153563A (US20030199744A1-20031023-C00003.png)
DE (1) DE2921363A1 (US20030199744A1-20031023-C00003.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164529A (ja) * 1986-09-30 1988-07-07 テキサス　インスツルメンツ　インコーポレイテッド プログラマブルシーケンス発生器

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215123A (ja) * 1982-06-07 1983-12-14 Advantest Corp 多相タイミング発生装置
JPS60254097A (ja) * 1984-05-30 1985-12-14 カシオ計算機株式会社 歪波形発生装置
DE3543471C1 (de) * 1985-12-09 1992-01-09 Nixdorf Computer Ag In integrierter Technik hergestellter Baustein zur Erstellung integrierter Schaltungen
FR2631502A1 (fr) * 1988-05-10 1989-11-17 Thomson Video Equip Circuit generateur et sequenceur de signaux logiques pour dispositif a transfert de charges
DE4225388C2 (de) * 1992-07-31 1996-08-14 Siemens Ag Schaltungsanordnung zur Synchronisierung von dezentralen Zählern
US8135975B2 (en) 2007-03-09 2012-03-13 Analog Devices, Inc. Software programmable timing architecture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1084763B (de) * 1957-01-16 1960-07-07 Emi Ltd Anordnung zur Ableitung von Impulsgruppen aus einer Hauptimpulsfolge
US2964657A (en) * 1958-06-13 1960-12-13 North American Aviation Inc Electronic commutator
DE1220475B (de) * 1964-06-12 1966-07-07 Ericsson Telefon Ab L M Schaltungsanordnung zur Erzeugung einer Impulsfolge, in der die Impulsflanken eine exakt definierte Zeitstellung haben
US3530434A (en) * 1967-06-14 1970-09-22 Sylvania Electric Prod Coded frequency vehicle identification system
US3566153A (en) * 1969-04-30 1971-02-23 Texas Instruments Inc Programmable sequential logic
US3631407A (en) * 1969-06-25 1971-12-28 Corning Glass Works Character memory of reduced size
BE757298A (fr) * 1969-12-10 1971-03-16 Sits Soc It Telecom Siemens Generateur numerique pouvant produire une serie de frequences discrete
US3671875A (en) * 1971-05-20 1972-06-20 Bell Telephone Labor Inc Digitally operated signal regenerator and timing circuit
US3893088A (en) * 1971-07-19 1975-07-01 Texas Instruments Inc Random access memory shift register system
JPS5538859B2 (US20030199744A1-20031023-C00003.png) * 1972-01-21 1980-10-07
US4032894A (en) * 1976-06-01 1977-06-28 International Business Machines Corporation Logic array with enhanced flexibility
US4221001A (en) * 1977-04-01 1980-09-02 Teletype Corporation Shift register suitable for controlling the energization of a multiwinding motor
JPS54110745A (en) * 1978-02-20 1979-08-30 Hitachi Ltd Timing signal generating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164529A (ja) * 1986-09-30 1988-07-07 テキサス　インスツルメンツ　インコーポレイテッド プログラマブルシーケンス発生器

Also Published As

Publication number Publication date
DE2921363A1 (de) 1980-01-24
JPS6323685B2 (US20030199744A1-20031023-C00003.png) 1988-05-17
US4431926A (en) 1984-02-14
DE2921363C2 (US20030199744A1-20031023-C00003.png) 1987-03-19

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