JPS5663676A - Pattern generator - Google Patents

Pattern generator

Info

Publication number
JPS5663676A
JPS5663676A JP13834579A JP13834579A JPS5663676A JP S5663676 A JPS5663676 A JP S5663676A JP 13834579 A JP13834579 A JP 13834579A JP 13834579 A JP13834579 A JP 13834579A JP S5663676 A JPS5663676 A JP S5663676A
Authority
JP
Japan
Prior art keywords
data
memory
circuit
pattern data
matrix
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13834579A
Other languages
Japanese (ja)
Inventor
Katsuji Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13834579A priority Critical patent/JPS5663676A/en
Publication of JPS5663676A publication Critical patent/JPS5663676A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To economize the capacity of a memory, by preparing normal, white removing, double and partial white removing pattern data from one dot pattern data stored in the dot matrix memory and a control pattern data, and making it unnecessary to store various data in the memory.
CONSTITUTION: A dot matrix data is read out from the dot matrix memory 1, it is provided to the control pattern data memory circuit 2, and at the same time it is provided to the logic negating circuit 3, the OR circuit 4, the exclusive "or" circuit 5 and the pattern selective circuit 6. And logic negation of the matrix data, OR of the control pattern data and the matrix data, and exclusive "or" of the matrix data and the pattern data are generated, and the matrix data, logic negation, OR and exclusive "or" are selected by the selective circuit 6 and are output so that normal, white removing, double and partial white removing pattern data can be prepared, and the capacity of the memory 1 is economized.
COPYRIGHT: (C)1981,JPO&Japio
JP13834579A 1979-10-26 1979-10-26 Pattern generator Pending JPS5663676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13834579A JPS5663676A (en) 1979-10-26 1979-10-26 Pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13834579A JPS5663676A (en) 1979-10-26 1979-10-26 Pattern generator

Publications (1)

Publication Number Publication Date
JPS5663676A true JPS5663676A (en) 1981-05-30

Family

ID=15219742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13834579A Pending JPS5663676A (en) 1979-10-26 1979-10-26 Pattern generator

Country Status (1)

Country Link
JP (1) JPS5663676A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816379A (en) * 1981-07-20 1983-01-31 Sharp Corp Output device for displaying or recording background pattern
JPS5816380A (en) * 1981-07-20 1983-01-31 Sharp Corp Output device for displaying or recording figure pattern
JPH0772845A (en) * 1994-07-06 1995-03-17 Casio Comput Co Ltd Character processor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5816379A (en) * 1981-07-20 1983-01-31 Sharp Corp Output device for displaying or recording background pattern
JPS5816380A (en) * 1981-07-20 1983-01-31 Sharp Corp Output device for displaying or recording figure pattern
JPH0772845A (en) * 1994-07-06 1995-03-17 Casio Comput Co Ltd Character processor

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