JPS54145581A - Driver circuit of clock device - Google Patents

Driver circuit of clock device

Info

Publication number
JPS54145581A
JPS54145581A JP5354378A JP5354378A JPS54145581A JP S54145581 A JPS54145581 A JP S54145581A JP 5354378 A JP5354378 A JP 5354378A JP 5354378 A JP5354378 A JP 5354378A JP S54145581 A JPS54145581 A JP S54145581A
Authority
JP
Japan
Prior art keywords
pulses
regulators
terminals
circuits
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5354378A
Other languages
Japanese (ja)
Inventor
Hiroichi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5354378A priority Critical patent/JPS54145581A/en
Publication of JPS54145581A publication Critical patent/JPS54145581A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Clocks (AREA)

Abstract

PURPOSE: To obtain stable outputs and achieve the improvement of reliability by making effective use of switching regulators through the use of photo couplers.
CONSTITUTION: A circuit P to which pulses b being a part of the reference pulses a from a master watch 1 are being supplied and a circuit M to which pulses c being the other part of the pulses a are being supplied are provided. The circuits P, M are provided with switching regulators 12, 17, photo couplers 11, 16 and control the terminals RC of the respective regulators based on the pulses b, c. Further one of the output terminals of the regulators is grounded, whereby the alternate pulse voltages of positive and negative of the normal voltage level having beforehand been set in the regulators are obtained at the sub-watch drive terminals 8a, 8b coupled with the circuits P and M, whereby a plurality of the sub-watches are driven.
COPYRIGHT: (C)1979,JPO&Japio
JP5354378A 1978-05-04 1978-05-04 Driver circuit of clock device Pending JPS54145581A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5354378A JPS54145581A (en) 1978-05-04 1978-05-04 Driver circuit of clock device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5354378A JPS54145581A (en) 1978-05-04 1978-05-04 Driver circuit of clock device

Publications (1)

Publication Number Publication Date
JPS54145581A true JPS54145581A (en) 1979-11-13

Family

ID=12945707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5354378A Pending JPS54145581A (en) 1978-05-04 1978-05-04 Driver circuit of clock device

Country Status (1)

Country Link
JP (1) JPS54145581A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59122586U (en) * 1983-02-07 1984-08-17 株式会社テイ，アイ，シイ・シチズン Polarized signal acquisition device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59122586U (en) * 1983-02-07 1984-08-17 株式会社テイ，アイ，シイ・シチズン Polarized signal acquisition device

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