JPS54142977A - Fabricating method for semiconductor device - Google Patents

Fabricating method for semiconductor device

Info

Publication number
JPS54142977A
JPS54142977A JP4980878A JP4980878A JPS54142977A JP S54142977 A JPS54142977 A JP S54142977A JP 4980878 A JP4980878 A JP 4980878A JP 4980878 A JP4980878 A JP 4980878A JP S54142977 A JPS54142977 A JP S54142977A
Authority
JP
Japan
Prior art keywords
pellet
semiconductor
projection
layer
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4980878A
Other languages
English (en)
Inventor
Kenji Akeyama
Nobukatsu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4980878A priority Critical patent/JPS54142977A/ja
Publication of JPS54142977A publication Critical patent/JPS54142977A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP4980878A 1978-04-28 1978-04-28 Fabricating method for semiconductor device Pending JPS54142977A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4980878A JPS54142977A (en) 1978-04-28 1978-04-28 Fabricating method for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4980878A JPS54142977A (en) 1978-04-28 1978-04-28 Fabricating method for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54142977A true JPS54142977A (en) 1979-11-07

Family

ID=12841423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4980878A Pending JPS54142977A (en) 1978-04-28 1978-04-28 Fabricating method for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54142977A (ja)

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