JPS54141560A - Method of forming epitaxial layer - Google Patents
Method of forming epitaxial layerInfo
- Publication number
- JPS54141560A JPS54141560A JP4850279A JP4850279A JPS54141560A JP S54141560 A JPS54141560 A JP S54141560A JP 4850279 A JP4850279 A JP 4850279A JP 4850279 A JP4850279 A JP 4850279A JP S54141560 A JPS54141560 A JP S54141560A
- Authority
- JP
- Japan
- Prior art keywords
- epitaxial layer
- forming epitaxial
- forming
- layer
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NLAANVRAGE7804268,A NL187414C (nl) | 1978-04-21 | 1978-04-21 | Werkwijze voor het aanbrengen van een epitaxiale laag. |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54141560A true JPS54141560A (en) | 1979-11-02 |
JPS5538819B2 JPS5538819B2 (US08197722-20120612-C00093.png) | 1980-10-07 |
Family
ID=19830695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4850279A Granted JPS54141560A (en) | 1978-04-21 | 1979-04-18 | Method of forming epitaxial layer |
Country Status (8)
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016213232A (ja) * | 2015-04-30 | 2016-12-15 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
JP2017005049A (ja) * | 2015-06-08 | 2017-01-05 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
WO2017169290A1 (ja) * | 2016-04-01 | 2017-10-05 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0671770B1 (en) * | 1993-02-09 | 2000-08-02 | GENERAL SEMICONDUCTOR, Inc. | Multilayer epitaxy for a silicon diode |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL288409A (US08197722-20120612-C00093.png) * | 1962-02-02 | |||
DE2547692C3 (de) * | 1975-10-24 | 1979-10-31 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen einer Halbleiteranordnung |
-
1978
- 1978-04-21 NL NLAANVRAGE7804268,A patent/NL187414C/xx not_active IP Right Cessation
-
1979
- 1979-04-12 CA CA325,479A patent/CA1134059A/en not_active Expired
- 1979-04-12 AU AU46046/79A patent/AU523988B2/en not_active Ceased
- 1979-04-18 GB GB7913398A patent/GB2019644B/en not_active Expired
- 1979-04-18 JP JP4850279A patent/JPS54141560A/ja active Granted
- 1979-04-18 IT IT21949/79A patent/IT1112317B/it active
- 1979-04-19 DE DE2915883A patent/DE2915883C2/de not_active Expired
- 1979-04-20 FR FR7910090A patent/FR2423865A1/fr active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016213232A (ja) * | 2015-04-30 | 2016-12-15 | 株式会社Sumco | エピタキシャルシリコンウェーハの製造方法 |
US10253429B2 (en) | 2015-04-30 | 2019-04-09 | Sumco Corporation | Method for manufacturing epitaxial silicon wafer |
JP2017005049A (ja) * | 2015-06-08 | 2017-01-05 | 信越半導体株式会社 | エピタキシャルウェーハの製造方法 |
WO2017169290A1 (ja) * | 2016-04-01 | 2017-10-05 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
JP2017188507A (ja) * | 2016-04-01 | 2017-10-12 | 信越半導体株式会社 | シリコンエピタキシャルウェーハの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE2915883C2 (de) | 1987-01-22 |
IT7921949A0 (it) | 1979-04-18 |
FR2423865A1 (fr) | 1979-11-16 |
AU523988B2 (en) | 1982-08-26 |
FR2423865B1 (US08197722-20120612-C00093.png) | 1984-07-27 |
DE2915883A1 (de) | 1979-10-31 |
CA1134059A (en) | 1982-10-19 |
IT1112317B (it) | 1986-01-13 |
AU4604679A (en) | 1979-10-25 |
NL7804268A (nl) | 1979-10-23 |
NL187414C (nl) | 1991-09-16 |
GB2019644B (en) | 1982-09-29 |
JPS5538819B2 (US08197722-20120612-C00093.png) | 1980-10-07 |
NL187414B (nl) | 1991-04-16 |
GB2019644A (en) | 1979-10-31 |
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