JPS54141560A - Method of forming epitaxial layer - Google Patents

Method of forming epitaxial layer

Info

Publication number
JPS54141560A
JPS54141560A JP4850279A JP4850279A JPS54141560A JP S54141560 A JPS54141560 A JP S54141560A JP 4850279 A JP4850279 A JP 4850279A JP 4850279 A JP4850279 A JP 4850279A JP S54141560 A JPS54141560 A JP S54141560A
Authority
JP
Japan
Prior art keywords
epitaxial layer
forming epitaxial
forming
layer
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4850279A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5538819B2 (US08197722-20120612-C00093.png
Inventor
Zakariasu Antoniusu Ma Paurusu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of JPS54141560A publication Critical patent/JPS54141560A/ja
Publication of JPS5538819B2 publication Critical patent/JPS5538819B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Drying Of Semiconductors (AREA)
JP4850279A 1978-04-21 1979-04-18 Method of forming epitaxial layer Granted JPS54141560A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NLAANVRAGE7804268,A NL187414C (nl) 1978-04-21 1978-04-21 Werkwijze voor het aanbrengen van een epitaxiale laag.

Publications (2)

Publication Number Publication Date
JPS54141560A true JPS54141560A (en) 1979-11-02
JPS5538819B2 JPS5538819B2 (US08197722-20120612-C00093.png) 1980-10-07

Family

ID=19830695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4850279A Granted JPS54141560A (en) 1978-04-21 1979-04-18 Method of forming epitaxial layer

Country Status (8)

Country Link
JP (1) JPS54141560A (US08197722-20120612-C00093.png)
AU (1) AU523988B2 (US08197722-20120612-C00093.png)
CA (1) CA1134059A (US08197722-20120612-C00093.png)
DE (1) DE2915883C2 (US08197722-20120612-C00093.png)
FR (1) FR2423865A1 (US08197722-20120612-C00093.png)
GB (1) GB2019644B (US08197722-20120612-C00093.png)
IT (1) IT1112317B (US08197722-20120612-C00093.png)
NL (1) NL187414C (US08197722-20120612-C00093.png)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016213232A (ja) * 2015-04-30 2016-12-15 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
JP2017005049A (ja) * 2015-06-08 2017-01-05 信越半導体株式会社 エピタキシャルウェーハの製造方法
WO2017169290A1 (ja) * 2016-04-01 2017-10-05 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0671770B1 (en) * 1993-02-09 2000-08-02 GENERAL SEMICONDUCTOR, Inc. Multilayer epitaxy for a silicon diode

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL288409A (US08197722-20120612-C00093.png) * 1962-02-02
DE2547692C3 (de) * 1975-10-24 1979-10-31 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zum Herstellen einer Halbleiteranordnung

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016213232A (ja) * 2015-04-30 2016-12-15 株式会社Sumco エピタキシャルシリコンウェーハの製造方法
US10253429B2 (en) 2015-04-30 2019-04-09 Sumco Corporation Method for manufacturing epitaxial silicon wafer
JP2017005049A (ja) * 2015-06-08 2017-01-05 信越半導体株式会社 エピタキシャルウェーハの製造方法
WO2017169290A1 (ja) * 2016-04-01 2017-10-05 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法
JP2017188507A (ja) * 2016-04-01 2017-10-12 信越半導体株式会社 シリコンエピタキシャルウェーハの製造方法

Also Published As

Publication number Publication date
DE2915883C2 (de) 1987-01-22
IT7921949A0 (it) 1979-04-18
FR2423865A1 (fr) 1979-11-16
AU523988B2 (en) 1982-08-26
FR2423865B1 (US08197722-20120612-C00093.png) 1984-07-27
DE2915883A1 (de) 1979-10-31
CA1134059A (en) 1982-10-19
IT1112317B (it) 1986-01-13
AU4604679A (en) 1979-10-25
NL7804268A (nl) 1979-10-23
NL187414C (nl) 1991-09-16
GB2019644B (en) 1982-09-29
JPS5538819B2 (US08197722-20120612-C00093.png) 1980-10-07
NL187414B (nl) 1991-04-16
GB2019644A (en) 1979-10-31

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