JPS54137935A - Four-bit square-law circuit - Google Patents

Four-bit square-law circuit

Info

Publication number
JPS54137935A
JPS54137935A JP4526678A JP4526678A JPS54137935A JP S54137935 A JPS54137935 A JP S54137935A JP 4526678 A JP4526678 A JP 4526678A JP 4526678 A JP4526678 A JP 4526678A JP S54137935 A JPS54137935 A JP S54137935A
Authority
JP
Japan
Prior art keywords
bit
bits
square
lowest
law
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4526678A
Other languages
Japanese (ja)
Inventor
Takashi Yokota
Masatsugu Kidode
Hidenori Shinoda
Haruo Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4526678A priority Critical patent/JPS54137935A/en
Publication of JPS54137935A publication Critical patent/JPS54137935A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/552—Powers or roots, e.g. Pythagorean sums

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To make an arithmetic speed high by reducing the number of input terminals of an integrated circuit by constituting a four-bit square-law circuit without using a multiplier. CONSTITUTION:The input consists of four bits A3 to A0, and the output of square- law calculation of eight bits B7 to B0. Here, A0 and B0 are the lowest bits, and A3 and B7 are the highest bits. The lowest bit B0 of the output is equal to the lowest bit A0 of the input. Then, B1 is ''0'' at any time. Bit B2 is AND between NOT of A0 and A1. Bit B3 is AND between A0 and OR-ELSE between A1 and A2. Bit B4 is AND between AO and OR-ELSE between A2 and A3. Bit B5 is AND BETWEEN AO and OR-ELSE between AND between A1 and OR-ELASE between A2 and A3, and AND among three inputs A0, A2 and A3. Bit B6 is AND between AND between A3 and NOT of A2, and AND amng three inputs A1, A2 and A3. Then, B7 is equal to AND between A2 and A3.
JP4526678A 1978-04-19 1978-04-19 Four-bit square-law circuit Pending JPS54137935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4526678A JPS54137935A (en) 1978-04-19 1978-04-19 Four-bit square-law circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4526678A JPS54137935A (en) 1978-04-19 1978-04-19 Four-bit square-law circuit

Publications (1)

Publication Number Publication Date
JPS54137935A true JPS54137935A (en) 1979-10-26

Family

ID=12714486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4526678A Pending JPS54137935A (en) 1978-04-19 1978-04-19 Four-bit square-law circuit

Country Status (1)

Country Link
JP (1) JPS54137935A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0037850A2 (en) * 1980-03-17 1981-10-21 Rockwell International Corporation A rom-based parallel digital arithmetic device
JPH0222734A (en) * 1988-07-11 1990-01-25 Nec Corp Square operating circuit
FR2700030A1 (en) * 1992-12-31 1994-07-01 Samsung Electronics Co Ltd Squaring calculation circuit.

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0037850A2 (en) * 1980-03-17 1981-10-21 Rockwell International Corporation A rom-based parallel digital arithmetic device
JPH0222734A (en) * 1988-07-11 1990-01-25 Nec Corp Square operating circuit
FR2700030A1 (en) * 1992-12-31 1994-07-01 Samsung Electronics Co Ltd Squaring calculation circuit.

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