JPS54121628A - Memory unit control system - Google Patents
Memory unit control systemInfo
- Publication number
- JPS54121628A JPS54121628A JP2938678A JP2938678A JPS54121628A JP S54121628 A JPS54121628 A JP S54121628A JP 2938678 A JP2938678 A JP 2938678A JP 2938678 A JP2938678 A JP 2938678A JP S54121628 A JPS54121628 A JP S54121628A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- initial writing
- cpu
- microprogram
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
Abstract
PURPOSE:To secure insertion of the initial writing program to an optional place in the microprogram by carrying out the initial writing to the memory via the microprogram of CPU when CPU decides the power supply making time. CONSTITUTION:Memory initializing signal 16 is transmitted from CPU at the power supply making time to perform the initial writing. After the writing action completed for all addresses of the memory, signal 19 indicating the end of the memory cycle is sent to CPU from timing generator circuit 8 to inform the end of operation. Accordingly, the microprogram has only to carry out the mode designation for the initial writing and the test for the memory contents of the power making signal (power-on signal) when the initial writing is carried out. Thus, the initial writing is given to the memory through the microprogram when CPU decides the power making time, ensuring the start of the initial writing with an optional timing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2938678A JPS54121628A (en) | 1978-03-15 | 1978-03-15 | Memory unit control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2938678A JPS54121628A (en) | 1978-03-15 | 1978-03-15 | Memory unit control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54121628A true JPS54121628A (en) | 1979-09-20 |
Family
ID=12274687
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2938678A Pending JPS54121628A (en) | 1978-03-15 | 1978-03-15 | Memory unit control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54121628A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2623650A1 (en) * | 1987-11-20 | 1989-05-26 | Sgs Thomson Microelectronics | MONOLITHIC ELECTRONIC COMPONENT PROVIDED WITH A COMMON DECODER FOR ITS BLIND MEMORY AND ITS PROCESSING MEMORY |
JPH02100526A (en) * | 1988-10-07 | 1990-04-12 | Fuji Electric Co Ltd | Individual identification method |
-
1978
- 1978-03-15 JP JP2938678A patent/JPS54121628A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2623650A1 (en) * | 1987-11-20 | 1989-05-26 | Sgs Thomson Microelectronics | MONOLITHIC ELECTRONIC COMPONENT PROVIDED WITH A COMMON DECODER FOR ITS BLIND MEMORY AND ITS PROCESSING MEMORY |
JPH01166156A (en) * | 1987-11-20 | 1989-06-30 | Sgs Thomson Microelectron Sa | Monolithic electronic device |
JPH02100526A (en) * | 1988-10-07 | 1990-04-12 | Fuji Electric Co Ltd | Individual identification method |
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