JPS54116162A - Variable frequency step down unit - Google Patents

Variable frequency step down unit

Info

Publication number
JPS54116162A
JPS54116162A JP2281578A JP2281578A JPS54116162A JP S54116162 A JPS54116162 A JP S54116162A JP 2281578 A JP2281578 A JP 2281578A JP 2281578 A JP2281578 A JP 2281578A JP S54116162 A JPS54116162 A JP S54116162A
Authority
JP
Japan
Prior art keywords
frequency
step down
fed
frequency step
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2281578A
Other languages
Japanese (ja)
Inventor
Yoshiharu Shigeta
Atsuyuki Takahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2281578A priority Critical patent/JPS54116162A/en
Publication of JPS54116162A publication Critical patent/JPS54116162A/en
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE: To simplify the circuit and to make small the circuit, by providing the variable frequency step down means having the frequency step down value of N and the fixed frequency step down means having the step down value M connected to it.
CONSTITUTION: The output of the local oscillator 9 having higher frequency fL than the output frequency fO of the voltage controlled oscillator 4, and the output of the oscillator 4 are fed to the frequency converter 5, the difference frequency between the both is fed to the fixed frequency step down unit 12, and one pulse is counted. Next, the frequency step down value is fed to the frequency step down units 6 to 8 from the selector 10 in common use with the display unit, N' demultiplication is made, and the demultiplied signal fv and the reference frequency fR from the reference frequency oscillator 1 are fed to the phase comparator 2, the signal detecting the phase difference of the both is fed back to the oscillator 4 via LPF 3 and the output frequency fO is obtained. Taking N'+1=N with the phase synchronous state, then fO=fL-NfR. When the frequency step down value N' is controlled with the selector 10 delivering binary decimal number corresponding to the complement of 9 to the display value, N becomes natural number continuous in the complement of 10.
COPYRIGHT: (C)1979,JPO&Japio
JP2281578A 1978-03-02 1978-03-02 Variable frequency step down unit Pending JPS54116162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2281578A JPS54116162A (en) 1978-03-02 1978-03-02 Variable frequency step down unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2281578A JPS54116162A (en) 1978-03-02 1978-03-02 Variable frequency step down unit

Publications (1)

Publication Number Publication Date
JPS54116162A true JPS54116162A (en) 1979-09-10

Family

ID=12093177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2281578A Pending JPS54116162A (en) 1978-03-02 1978-03-02 Variable frequency step down unit

Country Status (1)

Country Link
JP (1) JPS54116162A (en)

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