JPS5339867A - Packaging method of semiconductor device - Google Patents

Packaging method of semiconductor device

Info

Publication number
JPS5339867A
JPS5339867A JP11364976A JP11364976A JPS5339867A JP S5339867 A JPS5339867 A JP S5339867A JP 11364976 A JP11364976 A JP 11364976A JP 11364976 A JP11364976 A JP 11364976A JP S5339867 A JPS5339867 A JP S5339867A
Authority
JP
Japan
Prior art keywords
semiconductor device
packaging method
low cost
high density
small volume
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11364976A
Other languages
Japanese (ja)
Inventor
Junichiro Yamazaki
Ikuo Tomita
Eiichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11364976A priority Critical patent/JPS5339867A/en
Publication of JPS5339867A publication Critical patent/JPS5339867A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To perform packaging diversified kinds and small volume at low cost by using a sheet formed with carrier units at high density in matrix form.
COPYRIGHT: (C)1978,JPO&Japio
JP11364976A 1976-09-24 1976-09-24 Packaging method of semiconductor device Pending JPS5339867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11364976A JPS5339867A (en) 1976-09-24 1976-09-24 Packaging method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11364976A JPS5339867A (en) 1976-09-24 1976-09-24 Packaging method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5339867A true JPS5339867A (en) 1978-04-12

Family

ID=14617603

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11364976A Pending JPS5339867A (en) 1976-09-24 1976-09-24 Packaging method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5339867A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224634A (en) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224634A (en) * 1985-07-24 1987-02-02 Hitachi Vlsi Eng Corp Semiconductor device

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