JPS5317023B2 - - Google Patents

Info

Publication number
JPS5317023B2
JPS5317023B2 JP5178072A JP5178072A JPS5317023B2 JP S5317023 B2 JPS5317023 B2 JP S5317023B2 JP 5178072 A JP5178072 A JP 5178072A JP 5178072 A JP5178072 A JP 5178072A JP S5317023 B2 JPS5317023 B2 JP S5317023B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5178072A
Other versions
JPS4834447A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4834447A publication Critical patent/JPS4834447A/ja
Publication of JPS5317023B2 publication Critical patent/JPS5317023B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
JP5178072A 1971-08-31 1972-05-26 Expired JPS5317023B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17649571A 1971-08-31 1971-08-31

Publications (2)

Publication Number Publication Date
JPS4834447A JPS4834447A (ja) 1973-05-18
JPS5317023B2 true JPS5317023B2 (ja) 1978-06-05

Family

ID=22644580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5178072A Expired JPS5317023B2 (ja) 1971-08-31 1972-05-26

Country Status (7)

Country Link
US (1) US3771138A (ja)
JP (1) JPS5317023B2 (ja)
CA (1) CA954227A (ja)
DE (1) DE2224537C2 (ja)
FR (1) FR2151801A5 (ja)
GB (1) GB1378565A (ja)
IT (1) IT951839B (ja)

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001787A (en) * 1972-07-17 1977-01-04 International Business Machines Corporation Data processor for pattern recognition and the like
US3959777A (en) * 1972-07-17 1976-05-25 International Business Machines Corporation Data processor for pattern recognition and the like
JPS5039437A (ja) * 1973-08-10 1975-04-11
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
JPS5745684Y2 (ja) * 1974-05-20 1982-10-08
US4062058A (en) * 1976-02-13 1977-12-06 The United States Of America As Represented By The Secretary Of The Navy Next address subprocessor
SE435429B (sv) * 1977-04-26 1984-09-24 Ericsson Telefon Ab L M Anordning for att mot utgaende informationsflodesgrenar forgrena ett inkommande "pipeline"-informationsflode
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4236204A (en) * 1978-03-13 1980-11-25 Motorola, Inc. Instruction set modifier register
US4320453A (en) * 1978-11-02 1982-03-16 Digital House, Ltd. Dual sequencer microprocessor
JPS5585956A (en) * 1978-12-21 1980-06-28 Hitachi Ltd Information processor
US4295193A (en) * 1979-06-29 1981-10-13 International Business Machines Corporation Machine for multiple instruction execution
US4539635A (en) * 1980-02-11 1985-09-03 At&T Bell Laboratories Pipelined digital processor arranged for conditional operation
US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
DE3241357A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Vorrichtung zur mikrobefehls-bereitstellung fuer mindestens zwei unabhaengig arbeitende funktionseinheiten in einem integrierten, mikroprogrammierten elektronischen baustein und verfahren zu ihrem betrieb
US5093775A (en) * 1983-11-07 1992-03-03 Digital Equipment Corporation Microcode control system for digital data processing system
DE3419602A1 (de) * 1984-05-25 1985-11-28 Philips Patentverwaltung Gmbh, 2000 Hamburg Schaltungsanordnung zur verringerung der verzerrungen bei einem fm-quadraturdemodulator
US4631662A (en) * 1984-07-05 1986-12-23 The United States Of America As Represented By The Secretary Of The Navy Scanning alarm electronic processor
JPH0776917B2 (ja) * 1984-12-29 1995-08-16 ソニー株式会社 マイクロコンピユ−タ
JPH07107783B2 (ja) * 1985-05-30 1995-11-15 ソニー株式会社 エラ−情報チエツク装置
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
EP0239081B1 (en) * 1986-03-26 1995-09-06 Hitachi, Ltd. Pipelined data processor capable of decoding and executing plural instructions in parallel
US4773041A (en) * 1986-06-02 1988-09-20 Unisys Corporation System for executing a sequence of operation codes with some codes being executed out of order in a pipeline parallel processor
JPH0760388B2 (ja) * 1987-06-09 1995-06-28 三菱電機株式会社 パイプライン制御回路
GB8817912D0 (en) * 1988-07-27 1988-09-01 Int Computers Ltd Data processing apparatus
JPH0770961B2 (ja) * 1988-08-12 1995-07-31 日本電気株式会社 マイクロコンピュータ
JP2810068B2 (ja) * 1988-11-11 1998-10-15 株式会社日立製作所 プロセッサシステム、コンピュータシステム及び命令処理方法
US5127093A (en) * 1989-01-17 1992-06-30 Cray Research Inc. Computer look-ahead instruction issue control
JPH02306341A (ja) * 1989-02-03 1990-12-19 Nec Corp マイクロプロセッサ
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
JPH0476626A (ja) * 1990-07-13 1992-03-11 Toshiba Corp マイクロコンピュータ
US5151981A (en) * 1990-07-13 1992-09-29 International Business Machines Corporation Instruction sampling instrumentation
JP2908598B2 (ja) * 1991-06-06 1999-06-21 松下電器産業株式会社 情報処理装置
EP0547240B1 (en) * 1991-07-08 2000-01-12 Seiko Epson Corporation Risc microprocessor architecture implementing fast trap and exception state
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5961629A (en) * 1991-07-08 1999-10-05 Seiko Epson Corporation High performance, superscalar-based computer system with out-of-order instruction execution
EP1526446A3 (en) 1991-07-08 2007-04-04 Seiko Epson Corporation Extensible RISC microprocessor architecture
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
WO1993019416A1 (en) * 1992-03-25 1993-09-30 Zilog, Inc. Fast instruction decoding in a pipeline processor
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
DE69311330T2 (de) 1992-03-31 1997-09-25 Seiko Epson Corp Befehlsablauffolgeplanung von einem risc-superskalarprozessor
EP0638183B1 (en) 1992-05-01 1997-03-05 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
DE69329778T2 (de) * 1992-09-29 2001-04-26 Seiko Epson Corp System und verfahren zur handhabung von laden und/oder speichern in einem superskalar mikroprozessor
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
KR100292300B1 (ko) 1992-12-31 2001-09-17 야스카와 히데아키 레지스터재명명시스템및방법
US5925125A (en) * 1993-06-24 1999-07-20 International Business Machines Corporation Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
US5481743A (en) * 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US5872946A (en) * 1997-06-11 1999-02-16 Advanced Micro Devices, Inc. Instruction alignment unit employing dual instruction queues for high frequency instruction dispatch
US5918034A (en) * 1997-06-27 1999-06-29 Sun Microsystems, Inc. Method for decoupling pipeline stages
US5928355A (en) * 1997-06-27 1999-07-27 Sun Microsystems Incorporated Apparatus for reducing instruction issue stage stalls through use of a staging register
US6658447B2 (en) * 1997-07-08 2003-12-02 Intel Corporation Priority based simultaneous multi-threading
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6697935B1 (en) 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6044460A (en) * 1998-01-16 2000-03-28 Lsi Logic Corporation System and method for PC-relative address generation in a microprocessor with a pipeline architecture
US6317820B1 (en) 1998-06-05 2001-11-13 Texas Instruments Incorporated Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism
US6263424B1 (en) * 1998-08-03 2001-07-17 Rise Technology Company Execution of data dependent arithmetic instructions in multi-pipeline processors
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6542921B1 (en) * 1999-07-08 2003-04-01 Intel Corporation Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
US6357016B1 (en) 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6889319B1 (en) 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6496925B1 (en) 1999-12-09 2002-12-17 Intel Corporation Method and apparatus for processing an event occurrence within a multithreaded processor
US7051329B1 (en) * 1999-12-28 2006-05-23 Intel Corporation Method and apparatus for managing resources in a multithreaded processor
US7856633B1 (en) 2000-03-24 2010-12-21 Intel Corporation LRU cache replacement for a partitioned set associative cache
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US7139898B1 (en) 2000-11-03 2006-11-21 Mips Technologies, Inc. Fetch and dispatch disassociation apparatus for multistreaming processors
US7035998B1 (en) 2000-11-03 2006-04-25 Mips Technologies, Inc. Clustering stream and/or instruction queues for multi-streaming processors
US8024735B2 (en) 2002-06-14 2011-09-20 Intel Corporation Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
US7310722B2 (en) * 2003-12-18 2007-12-18 Nvidia Corporation Across-thread out of order instruction dispatch in a multithreaded graphics processor
US20060229638A1 (en) * 2005-03-29 2006-10-12 Abrams Robert M Articulating retrieval device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611307A (en) * 1969-04-03 1971-10-05 Ibm Execution unit shared by plurality of arrays of virtual processors

Also Published As

Publication number Publication date
IT951839B (it) 1973-07-10
DE2224537A1 (de) 1973-03-08
CA954227A (en) 1974-09-03
US3771138A (en) 1973-11-06
GB1378565A (en) 1974-12-27
DE2224537C2 (de) 1985-01-17
JPS4834447A (ja) 1973-05-18
FR2151801A5 (ja) 1973-04-20

Similar Documents

Publication Publication Date Title
FR2151801A5 (ja)
FR2198661A5 (ja)
FR2129463A5 (ja)
AU2658571A (ja)
AU2691671A (ja)
AU2485671A (ja)
AU2564071A (ja)
AU2742671A (ja)
AU2894671A (ja)
AU2684071A (ja)
AU2684171A (ja)
AU2938071A (ja)
AU2755871A (ja)
AU2837671A (ja)
AU2854371A (ja)
AU2740271A (ja)
AU2726271A (ja)
AU2724971A (ja)
AU2706571A (ja)
AU2875571A (ja)
AU2503871A (ja)
AU2880771A (ja)
AU2669471A (ja)
AU2885171A (ja)
AU2486471A (ja)