JPS5267966A - Manufacture of semiconductor unit - Google Patents

Manufacture of semiconductor unit

Info

Publication number
JPS5267966A
JPS5267966A JP14425175A JP14425175A JPS5267966A JP S5267966 A JPS5267966 A JP S5267966A JP 14425175 A JP14425175 A JP 14425175A JP 14425175 A JP14425175 A JP 14425175A JP S5267966 A JPS5267966 A JP S5267966A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor unit
silver
ceducible
eduction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14425175A
Other languages
Japanese (ja)
Inventor
Takashi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14425175A priority Critical patent/JPS5267966A/en
Publication of JPS5267966A publication Critical patent/JPS5267966A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)

Abstract

PURPOSE: To prevent current leak short circuit due to silver eduction by coating ceducible solution on electrode lead or silver plate surface after attachment of chip to heat discharge board and completing wire bonding.
COPYRIGHT: (C)1977,JPO&Japio
JP14425175A 1975-12-03 1975-12-03 Manufacture of semiconductor unit Pending JPS5267966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14425175A JPS5267966A (en) 1975-12-03 1975-12-03 Manufacture of semiconductor unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14425175A JPS5267966A (en) 1975-12-03 1975-12-03 Manufacture of semiconductor unit

Publications (1)

Publication Number Publication Date
JPS5267966A true JPS5267966A (en) 1977-06-06

Family

ID=15357741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14425175A Pending JPS5267966A (en) 1975-12-03 1975-12-03 Manufacture of semiconductor unit

Country Status (1)

Country Link
JP (1) JPS5267966A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5252783A (en) * 1992-02-10 1993-10-12 Motorola, Inc. Semiconductor package
WO1998035382A1 (en) * 1997-02-10 1998-08-13 Matsushita Electronics Corporation Resin sealed semiconductor device and method for manufacturing the same
US6126885A (en) * 1997-06-27 2000-10-03 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5252783A (en) * 1992-02-10 1993-10-12 Motorola, Inc. Semiconductor package
WO1998035382A1 (en) * 1997-02-10 1998-08-13 Matsushita Electronics Corporation Resin sealed semiconductor device and method for manufacturing the same
US6291274B1 (en) 1997-02-10 2001-09-18 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device and method for manufacturing the same
US6126885A (en) * 1997-06-27 2000-10-03 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device
US6258314B1 (en) 1997-06-27 2001-07-10 Matsushita Electronics Corporation Method for manufacturing resin-molded semiconductor device

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