JPS5252372A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5252372A
JPS5252372A JP12804875A JP12804875A JPS5252372A JP S5252372 A JPS5252372 A JP S5252372A JP 12804875 A JP12804875 A JP 12804875A JP 12804875 A JP12804875 A JP 12804875A JP S5252372 A JPS5252372 A JP S5252372A
Authority
JP
Japan
Prior art keywords
semiconductor device
bonding
circuits
selecting
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12804875A
Other languages
Japanese (ja)
Inventor
Junji Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12804875A priority Critical patent/JPS5252372A/en
Publication of JPS5252372A publication Critical patent/JPS5252372A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To improve yield of semiconductor devices by selecting among the elements or circuits of different characteristics those having desired characteristics and by bonding them.
COPYRIGHT: (C)1977,JPO&Japio
JP12804875A 1975-10-24 1975-10-24 Semiconductor device Pending JPS5252372A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12804875A JPS5252372A (en) 1975-10-24 1975-10-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12804875A JPS5252372A (en) 1975-10-24 1975-10-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5252372A true JPS5252372A (en) 1977-04-27

Family

ID=14975205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12804875A Pending JPS5252372A (en) 1975-10-24 1975-10-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5252372A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881029A (en) * 1985-09-30 1989-11-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit devices and methods for testing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4840670A (en) * 1971-09-30 1973-06-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4840670A (en) * 1971-09-30 1973-06-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881029A (en) * 1985-09-30 1989-11-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit devices and methods for testing same

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