JPS5171641A - - Google Patents
Info
- Publication number
- JPS5171641A JPS5171641A JP50134210A JP13421075A JPS5171641A JP S5171641 A JPS5171641 A JP S5171641A JP 50134210 A JP50134210 A JP 50134210A JP 13421075 A JP13421075 A JP 13421075A JP S5171641 A JPS5171641 A JP S5171641A
- Authority
- JP
- Japan
- Prior art keywords
- memory module
- address
- marked
- store
- faulty
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003550 marker Substances 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05D—SYSTEMS FOR CONTROLLING OR REGULATING NON-ELECTRIC VARIABLES
- G05D13/00—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover
- G05D13/08—Control of linear speed; Control of angular speed; Control of acceleration or deceleration, e.g. of a prime mover without auxiliary power
- G05D13/10—Centrifugal governors with fly-weights
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/54558—Redundancy, stand-by
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Exchange Systems With Centralized Control (AREA)
- Hardware Redundancy (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA213,526A CA1053352A (en) | 1974-11-12 | 1974-11-12 | Method for providing a substitute memory module in a data processing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5171641A true JPS5171641A (nl) | 1976-06-21 |
JPS5412373B2 JPS5412373B2 (nl) | 1979-05-22 |
Family
ID=4101603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13421075A Expired JPS5412373B2 (nl) | 1974-11-12 | 1975-11-10 |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS5412373B2 (nl) |
CA (1) | CA1053352A (nl) |
DE (1) | DE2550805A1 (nl) |
FR (1) | FR2291544A1 (nl) |
GB (1) | GB1512220A (nl) |
NL (1) | NL7512713A (nl) |
SE (2) | SE413949B (nl) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2741379A1 (de) * | 1977-09-14 | 1979-03-15 | Siemens Ag | Rechnersystem |
JPS5580164A (en) * | 1978-12-13 | 1980-06-17 | Fujitsu Ltd | Main memory constitution control system |
JPS6272138A (ja) * | 1985-09-26 | 1987-04-02 | Hitachi Electronics Eng Co Ltd | 検査装置のウエハ位置決め保持装置 |
FR2643993B1 (fr) * | 1989-03-03 | 1991-05-17 | Bull Sa | Procede pour remplacer des modules memoire dans un systeme informatique et systeme informatique pour la mise en oeuvre du procede |
US7139942B2 (en) * | 2003-07-21 | 2006-11-21 | Sun Microsystems, Inc. | Method and apparatus for memory redundancy and recovery from uncorrectable errors |
-
1974
- 1974-11-12 CA CA213,526A patent/CA1053352A/en not_active Expired
-
1975
- 1975-10-29 GB GB44698/75A patent/GB1512220A/en not_active Expired
- 1975-10-30 NL NL7512713A patent/NL7512713A/nl not_active Application Discontinuation
- 1975-11-10 JP JP13421075A patent/JPS5412373B2/ja not_active Expired
- 1975-11-12 DE DE19752550805 patent/DE2550805A1/de not_active Withdrawn
- 1975-11-12 FR FR7534509A patent/FR2291544A1/fr not_active Withdrawn
- 1975-11-12 SE SE7512711-8A patent/SE413949B/xx not_active IP Right Cessation
-
1977
- 1977-09-07 SE SE7512711A patent/SE413948B/xx unknown
Also Published As
Publication number | Publication date |
---|---|
FR2291544A1 (fr) | 1976-06-11 |
GB1512220A (en) | 1978-05-24 |
DE2550805A1 (de) | 1976-05-13 |
NL7512713A (nl) | 1976-05-14 |
SE7512711L (sv) | 1976-05-13 |
JPS5412373B2 (nl) | 1979-05-22 |
SE413949B (sv) | 1980-06-30 |
SE413948B (sv) | 1980-06-30 |
SE7710060L (sv) | 1979-03-08 |
CA1053352A (en) | 1979-04-24 |
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