JPS51126068A - Manufacturing method of semi-conductor equipment - Google Patents

Manufacturing method of semi-conductor equipment

Info

Publication number
JPS51126068A
JPS51126068A JP50049710A JP4971075A JPS51126068A JP S51126068 A JPS51126068 A JP S51126068A JP 50049710 A JP50049710 A JP 50049710A JP 4971075 A JP4971075 A JP 4971075A JP S51126068 A JPS51126068 A JP S51126068A
Authority
JP
Japan
Prior art keywords
semi
manufacturing
conductor equipment
adhering
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50049710A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5311816B2 (https=
Inventor
Eiji Yamamoto
Hajime Murakami
Hiroshi Tsuneno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50049710A priority Critical patent/JPS51126068A/ja
Publication of JPS51126068A publication Critical patent/JPS51126068A/ja
Publication of JPS5311816B2 publication Critical patent/JPS5311816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Die Bonding (AREA)
JP50049710A 1975-04-25 1975-04-25 Manufacturing method of semi-conductor equipment Granted JPS51126068A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50049710A JPS51126068A (en) 1975-04-25 1975-04-25 Manufacturing method of semi-conductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50049710A JPS51126068A (en) 1975-04-25 1975-04-25 Manufacturing method of semi-conductor equipment

Publications (2)

Publication Number Publication Date
JPS51126068A true JPS51126068A (en) 1976-11-02
JPS5311816B2 JPS5311816B2 (https=) 1978-04-25

Family

ID=12838734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50049710A Granted JPS51126068A (en) 1975-04-25 1975-04-25 Manufacturing method of semi-conductor equipment

Country Status (1)

Country Link
JP (1) JPS51126068A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394072U (https=) * 1976-12-28 1978-08-01
JPS54160564U (https=) * 1978-04-28 1979-11-09
JPS5618480A (en) * 1979-07-23 1981-02-21 Toshiba Corp Manufacture of display device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394072U (https=) * 1976-12-28 1978-08-01
JPS54160564U (https=) * 1978-04-28 1979-11-09
JPS5618480A (en) * 1979-07-23 1981-02-21 Toshiba Corp Manufacture of display device

Also Published As

Publication number Publication date
JPS5311816B2 (https=) 1978-04-25

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