JPS501513B1 - - Google Patents

Info

Publication number
JPS501513B1
JPS501513B1 JP43090252A JP9025268A JPS501513B1 JP S501513 B1 JPS501513 B1 JP S501513B1 JP 43090252 A JP43090252 A JP 43090252A JP 9025268 A JP9025268 A JP 9025268A JP S501513 B1 JPS501513 B1 JP S501513B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP43090252A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP43090252A priority Critical patent/JPS501513B1/ja
Priority to US04/881,822 priority patent/US4009484A/en
Priority to DE19691961739 priority patent/DE1961739A1/de
Priority to FR696942419A priority patent/FR2025862B1/fr
Priority to NL6918519A priority patent/NL6918519A/xx
Publication of JPS501513B1 publication Critical patent/JPS501513B1/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/611Combinations of BJTs and one or more of diodes, resistors or capacitors
    • H10D84/613Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
    • H10P14/2905Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34Deposited materials, e.g. layers
    • H10P14/3402Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/041Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP43090252A 1968-12-11 1968-12-11 Pending JPS501513B1 (enExample)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP43090252A JPS501513B1 (enExample) 1968-12-11 1968-12-11
US04/881,822 US4009484A (en) 1968-12-11 1969-12-03 Integrated circuit isolation using gold-doped polysilicon
DE19691961739 DE1961739A1 (de) 1968-12-11 1969-12-09 Halbleitervorrichtung und Verfahren zu ihrer Herstellung
FR696942419A FR2025862B1 (enExample) 1968-12-11 1969-12-09
NL6918519A NL6918519A (enExample) 1968-12-11 1969-12-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP43090252A JPS501513B1 (enExample) 1968-12-11 1968-12-11

Publications (1)

Publication Number Publication Date
JPS501513B1 true JPS501513B1 (enExample) 1975-01-18

Family

ID=13993292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP43090252A Pending JPS501513B1 (enExample) 1968-12-11 1968-12-11

Country Status (5)

Country Link
US (1) US4009484A (enExample)
JP (1) JPS501513B1 (enExample)
DE (1) DE1961739A1 (enExample)
FR (1) FR2025862B1 (enExample)
NL (1) NL6918519A (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3929529A (en) * 1974-12-09 1975-12-30 Ibm Method for gettering contaminants in monocrystalline silicon
GB1572703A (en) * 1975-12-10 1980-07-30 Tokyo Shibaura Electric Co Semiconductor device and method of producing a semiconductor device
FR2335951A1 (fr) * 1975-12-19 1977-07-15 Radiotechnique Compelec Dispositif semiconducteur a surface passivee et procede d'obtention de la structure de passivation
US4184172A (en) * 1976-12-06 1980-01-15 Massachusetts Institute Of Technology Dielectric isolation using shallow oxide and polycrystalline silicon
JPS5951743B2 (ja) * 1978-11-08 1984-12-15 株式会社日立製作所 半導体集積装置
US4262299A (en) * 1979-01-29 1981-04-14 Rca Corporation Semiconductor-on-insulator device and method for its manufacture
US4283235A (en) * 1979-07-27 1981-08-11 Massachusetts Institute Of Technology Dielectric isolation using shallow oxide and polycrystalline silicon utilizing selective oxidation
US4231819A (en) * 1979-07-27 1980-11-04 Massachusetts Institute Of Technology Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step
US4353086A (en) * 1980-05-07 1982-10-05 Bell Telephone Laboratories, Incorporated Silicon integrated circuits
JPH01289264A (ja) * 1988-05-17 1989-11-21 Toshiba Corp 半導体装置
DE4236300A1 (de) * 1992-10-28 1994-05-11 Telefunken Microelectron Verfahren zur Herstellung von Halbleiterbauelementen mit geringer Schaltzeit
KR0175000B1 (ko) * 1994-12-14 1999-02-01 윤종용 전자파 억제구조를 갖는 반도체 소자
JP4351869B2 (ja) * 2003-06-10 2009-10-28 隆 河東田 半導体を用いた電子デバイス
US7505309B2 (en) * 2005-04-20 2009-03-17 Micron Technology, Inc. Static RAM memory cell with DNR chalcogenide devices and method of forming

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1145075A (en) * 1965-04-07 1969-03-12 Matsushita Electric Industrial Co Ltd Semiconductor device
FR1475243A (fr) * 1965-04-07 1967-03-31 Matsushita Electric Industrial Co Ltd Dispositif semiconducteur
US3475661A (en) * 1966-02-09 1969-10-28 Sony Corp Semiconductor device including polycrystalline areas among monocrystalline areas
US3440114A (en) * 1966-10-31 1969-04-22 Texas Instruments Inc Selective gold doping for high resistivity regions in silicon
US3447235A (en) * 1967-07-21 1969-06-03 Raytheon Co Isolated cathode array semiconductor

Also Published As

Publication number Publication date
FR2025862A1 (enExample) 1970-09-11
NL6918519A (enExample) 1970-06-15
DE1961739A1 (de) 1970-06-18
FR2025862B1 (enExample) 1973-05-25
US4009484A (en) 1977-02-22

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