GB1572703A - Semiconductor device and method of producing a semiconductor device - Google Patents
Semiconductor device and method of producing a semiconductor device Download PDFInfo
- Publication number
- GB1572703A GB1572703A GB5140576A GB5140576A GB1572703A GB 1572703 A GB1572703 A GB 1572703A GB 5140576 A GB5140576 A GB 5140576A GB 5140576 A GB5140576 A GB 5140576A GB 1572703 A GB1572703 A GB 1572703A
- Authority
- GB
- United Kingdom
- Prior art keywords
- region
- impurity
- conductivity type
- collector
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims description 37
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 40
- 239000012535 impurity Substances 0.000 claims description 38
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 101001005711 Homo sapiens MARVEL domain-containing protein 2 Proteins 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Bipolar Transistors (AREA)
Description
(54) SEMICONDUCTOR DEVICE AND METHOD
OF PRODUCING A SEMICONDUCTOR DEVICE
(71) We, TOKYO SHIBAURA ELEC
TRIC COMPANY LIMITED, a Japanese corporation, of 72 Horikawa-cho, Saiwaiku, Kawasaki-shi, Japan, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:
This invention relates to a semiconductor device and to a method of producing a semiconductor device.
Appended Figure 1 shows a transistor as an example of conventional semiconductor device. In the drawing, reference numeral 1 denotes an isolated N-type collector region within a silicon substrate 2. A P-type base region 3 is formed within the collector region 1 by diffusing boron at 1200"C down to a predetermined depth. Further, an
N±type emitter region 4 is formed within the base region 3 by diffusing phosphorus at 11000C in a high concentration. Likewise, an N±type low resistance region 5 is formed within the N-type collector region 1 by diffusing a high concentration of a donor impurity for ease in forming ohmic contact with a collector electrode 6. Incidentally, reference numerals 7, 8, 9 and 10 denote respectively a base electrode, an emitter electrode, a surface insulation layer and an N±type buried layer.
A conventional silicon bipolar transistor thus constructed presents a so-called "Emitter push" effect because the emitter region 4 is formed by diffusing a high concentration of impurity at a high temperature, resulting in occurrences of a lage number of lattice defects and strains of the silicon crystal constituting the transistor. It follows that deterioration of electric properties is caused including a marked increase in I/f noise or pulse-like noise generation.
An object of this invention is to provide a semiconductor device having lattice defects on the crystal derived from the diffusion of a high concentration of impurity to a lesser extent than those of the transistor described above.
According to one aspect of this invention, there is provided a method of producting a semiconductor device comprising the steps of forming a polycrystalline silicon region of one conductivity type on the surface of a single crystalline silicon region of the opposite conductivity type, and heating the polycrystalline silicon region to a temperature at which the impurity of the polycrystalline silicon region is diffused into the single crystalline silicon region to at most a negligible extent, so as to activate the impurity of the polycrystalline silicon region.
Activation of the impurity ensures that the impurity enters the lattice positions of the polycrystalline silicon region.
This aspect of this invention further provides a semiconductor device produced by the method of the preceding paragraph and having a p-n junction formed between a single crystalline silicon region of one conductivity type and a polycrystalline silicon region of the opposite conductivity type formed on the surface of the single crystalline silicon region, said single crystalline region being substantially free from impurity diffused from the polycrystalline region.
According to another aspect of this invention there is provided a method of producing a transistor comprising the steps of forming a collector region of one conductiv ity type consiting of a single crystalline silicon, forming a base region of the opposite conductivity type within the collector region, forming an emitter region of the one conductivity type consisting of a polycrystalline silicon on the surface of the base region, and heating the emitter region to a temperature at which the impurity of the emitter region is diffused into the base region to at most. a negligible extent, so as to activate the impurity of the emitter region.
This further aspect of this invention further provides a transistor produced by the method of the preceding paragraph and comprising a collector region of one conductivity type formed of a single crystalline silicon, a base region of the opposite conductivity type formed within the collector region, and an emitter region of the one conductivity type formed on the surface of the base region, said emitter region consisting of polycrystalline silicon and the base region being substantially free from impurity diffused from the emitter region.
A transistor according to this invention may have a low I/f noise generation.
Preferably, a low resistance region for forming ohmic contact with a collector electrode, said region consisting of the same polycrystalline silicon as for the emitter region is formed on the surface of the collector region.
Preferably, the impurity concentration of the emitter region is higher than that of the
collector region.
The semiconductor device may also be a diode.
An embodiment of this invention will now be described with reference to the accompanying drawings, in which:
Figure 1 shows a cross section of a conventional transistor;
Figures 2(A) to 2 (F) are cross sectional views showing manufacturing steps of a transistor according to this invention; and
Figure 3 is a graph showing the I/f noise property of a transistor according to this invention in comparison with a conventional one.
Referring to Figure 2(A), reference numeral 11 denotes an N-type collector region isolated from the remaining Si substrate region. Specifically, the N-type collector region 11 may be formed by, for example, the method comprising the steps of forming an N±type buried layer 13 by diffusion on a
P-type silicon substrate 12, forming an
N-type layer on the surface of the silicon substrate 12 by epitaxial growth method, and forming a pair of P-type diffusion layers 14, 14 vertically extending through the
N-type epitaxial layer so as to isolate the
N-type collector region 11.
A SiO2 film 15 is formed on the entire surface of the epitaxial layer and, then, selectively removed to provide an opening through which is diffused a P-type impurity into the N-type collector region 11 so as to form a P-type base region 16 within the collector region. A fresh SiO2 film 17 is then formed to cover the entire surface area including the remaining SiO2 film 15 and the base region 16.
As shown in Figure 2(B), the SiO2 films 15 and 17 are then selectively removed by photo-etching so as to partly expose the base region 16 and the collector region 11.
Further, an N-type poly-Si layer 18 is formed by vapor growth method as shown in
Figure 2(C). It is seen that the poly-Si layer 18 covers the exposed portions of the base and collector regions and the remaining
SiO2 film 17. The poly-Si layer 18 is doped with a high concentration of at least one kind of N-type impurity. On the surface of the poly-Si layer 18 is formed a SiO2 film 19 by chemical vapor deposition as shown in
Figure 2(C). A heating step for activating the impurity of the poly-Si layer 18 follows the step of forming the SiO2 film 19. In this case, the temperature should be controlled so as not to allow the impurity of the poly-Si layer 18 to be diffused substantially into the base region 16. To this end, the heating should be effected at temperatures ranging from about 500 to 10000C, preferably at about 800"C. Incidentally, the word "substantially" mentioned above implies that the impurity of the poly-Si layer 18 scarcely enters the base region 16 or the amount of the impurity diffused from the poly-Si layer 18 to the base region 16 is negligibly small.
With the SiO2 film 19 used as a mask, the poly-Si layer 18 is selectively removed by plasma etching so as to form an emitter region 20 and an N-type layer 21 for ohmic contact with a collector electrode as shown in Figure 2(D). Naturally, the emitter region 20 and the N±type layer 21 consist of poly-Si. Then, a passivation film 22 such as a PSG (phosphorus silicate glass) film, a silicon nitride (Si3N4) film etc. is formed to cover the emitter region 20, the N±type layer 21 and the remaining SiO2 film 17.
The passivation film 22 as well as the SiO2 film beneath the film 22 are selectively removed by photo-etching so as to expose a part of the emitter region 20, a part of the base region 16 and the N±type layer 21 for the subsequent formation of a metal layer 23 acting as the electrode as shown in Figure 2(E).
It is preferred that the metal layer 23 be composed of a substrate metal layer 23a consisting of chromium, or titanium, and an aluminum layer 23b formed on the metal layer 23a. Aluminum has a large diffusion coefficient into poly-Si, whereas the diffusion of chromium, or titanium, is sufficiently small. It follows that the substrate layer 23a serves to prevent the aluminum from being diffused into the poly-Si.
Finally, undesired portions of the metal layer 23 are selectively removed by photoetching so as to provide electrodes at desired points as shown in Figure 2(F).
Figure 3 shows that the illustrated transistor according to this invention is markedly superior to the conventional transistor as shown in Figure 1 in l/f noise property. In
Figure 3, the noise figure (NF) is plotted in the ordinate and the frequency (Hz) in the abscissa. The dotted line represents the coventional transistor and the solid line denotes the illustrated transistor according to this invention. The values shown in the graph were obtained under the conditions:
Rg (signal source resistance) = 1 kQ Ic (collector current) = 1 mA
VCE (collector-emitter voltage) = 5V This invention reduces the occurrence of the lattice defect of the silicon crystal derived from the diffusion of a high concentration of impurities. It follows that a semiconductor device, for example, a transistor, based on the technical idea of this invention can be lower in I/f noise than the conventional transistor having its emitter region formed by diffusing a high concentration of impurity.
WHAT WE CLAIM IS:
1. A method of producing a semiconductor device comprising the steps of forming a polycrystalline silicon region of one conductivity type on the surface of a single crystalline silicon region of the opposite conductivity type, and heating the polycrystalline silicon region to a temperature at which the impurity of the polycrystalline silicon region is diffused into the single crystalline silicon region to at most a negligible extent, so as to activate the impurity of the polycrystalline silicon region.
2. A method according to claim 1, wherein the heating is effected at temperatures ranging from about 500or to about 1000"C.
3. A semiconductor device produced by a method according to claim 1 or claim 2 and having a p-n junction formed between a single crystalline silicon region of one conductivity type and a polycrystalline silicon region of the opposite conductivity type formed on the surface of the single crystalline silicon region, said single crystalline region being substantially free from impurity diffused from the polycrystalline region.
4. A method of producing a transistor comprising the steps of forming a collector region of one conductivity type consisting of a single crystalline silicon, forming a base region of the opposite conductivity type within the collector region, forming an emitter region of the one conductivity type consisting of a polycrystalline silicon on the surface of the base region, and heating the emitter region to a temperature at which the impurity of the emitter region is diffused into the base region to at most, a negligible extent, so as to activate the impurity of the emitter region.
5. A method according to claim 4, wherein the collector region is formed with
in a silicon substrate by isolation diffusion.
6. A method according to claim 4,
wherein the impurity concentration of the
emitter region is higher than that of the
collector region.
7. A method according to claim 4, wherein a polycrystalline silicon low resist
ance region for ohmic contact with a collector electrode is formed on the surface of the collector region at the time of forming the emitter region.
8. A method according to claim 4, wherein the heating for activating the emitter region is effected at temperatures ranging from about 500"C to about 1000"C.
9. A method according to claim 4, wherein the base region is formed by diffusing an impurity into the collector region.
10. A method according to claim 4, wherein the polycrystalline silicon emitter region is formed by vapor growth method.
11. A transistor produced by a method according to any of claims 4 to 10 and comprising a collector region of one conductivity type formed of a single crystalline silicon, a base region of the opposite conductivity type formed within the collector region, and an emitter region of the one conductivity type formed on the surface of the base region, said emitter region consisting of polycrystalline silicon and the base region being substantially free from impurity diffused from the emitter region.
12. A semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
13. A method of producing a semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
**WARNING** end of DESC field may overlap start of CLMS **.
Claims (13)
1. A method of producing a semiconductor device comprising the steps of forming a polycrystalline silicon region of one conductivity type on the surface of a single crystalline silicon region of the opposite conductivity type, and heating the polycrystalline silicon region to a temperature at which the impurity of the polycrystalline silicon region is diffused into the single crystalline silicon region to at most a negligible extent, so as to activate the impurity of the polycrystalline silicon region.
2. A method according to claim 1, wherein the heating is effected at temperatures ranging from about 500or to about 1000"C.
3. A semiconductor device produced by a method according to claim 1 or claim 2 and having a p-n junction formed between a single crystalline silicon region of one conductivity type and a polycrystalline silicon region of the opposite conductivity type formed on the surface of the single crystalline silicon region, said single crystalline region being substantially free from impurity diffused from the polycrystalline region.
4. A method of producing a transistor comprising the steps of forming a collector region of one conductivity type consisting of a single crystalline silicon, forming a base region of the opposite conductivity type within the collector region, forming an emitter region of the one conductivity type consisting of a polycrystalline silicon on the surface of the base region, and heating the emitter region to a temperature at which the impurity of the emitter region is diffused into the base region to at most, a negligible extent, so as to activate the impurity of the emitter region.
5. A method according to claim 4, wherein the collector region is formed with
in a silicon substrate by isolation diffusion.
6. A method according to claim 4,
wherein the impurity concentration of the
emitter region is higher than that of the
collector region.
7. A method according to claim 4, wherein a polycrystalline silicon low resist
ance region for ohmic contact with a collector electrode is formed on the surface of the collector region at the time of forming the emitter region.
8. A method according to claim 4, wherein the heating for activating the emitter region is effected at temperatures ranging from about 500"C to about 1000"C.
9. A method according to claim 4, wherein the base region is formed by diffusing an impurity into the collector region.
10. A method according to claim 4, wherein the polycrystalline silicon emitter region is formed by vapor growth method.
11. A transistor produced by a method according to any of claims 4 to 10 and comprising a collector region of one conductivity type formed of a single crystalline silicon, a base region of the opposite conductivity type formed within the collector region, and an emitter region of the one conductivity type formed on the surface of the base region, said emitter region consisting of polycrystalline silicon and the base region being substantially free from impurity diffused from the emitter region.
12. A semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
13. A method of producing a semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14636075A JPS5270761A (en) | 1975-12-10 | 1975-12-10 | Semiconductor device |
| JP797276A JPS5291654A (en) | 1976-01-29 | 1976-01-29 | Semiconductor device |
| JP797376A JPS5291655A (en) | 1976-01-29 | 1976-01-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1572703A true GB1572703A (en) | 1980-07-30 |
Family
ID=27277825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB5140576A Expired GB1572703A (en) | 1975-12-10 | 1976-12-09 | Semiconductor device and method of producing a semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| DE (1) | DE2656158A1 (en) |
| GB (1) | GB1572703A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL7713051A (en) * | 1977-11-28 | 1979-05-30 | Philips Nv | SEMI-CONDUCTOR DEVICE WITH A PERMANENT MEMORY AND METHOD FOR MANUFACTURE OF SUCH SEMI-CONDUCTOR DEVICE. |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS501513B1 (en) * | 1968-12-11 | 1975-01-18 |
-
1976
- 1976-12-09 GB GB5140576A patent/GB1572703A/en not_active Expired
- 1976-12-10 DE DE19762656158 patent/DE2656158A1/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| DE2656158A1 (en) | 1977-06-23 |
| DE2656158C2 (en) | 1987-10-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| 746 | Register noted 'licences of right' (sect. 46/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |