JPS4996645A - - Google Patents

Info

Publication number
JPS4996645A
JPS4996645A JP48121539A JP12153973A JPS4996645A JP S4996645 A JPS4996645 A JP S4996645A JP 48121539 A JP48121539 A JP 48121539A JP 12153973 A JP12153973 A JP 12153973A JP S4996645 A JPS4996645 A JP S4996645A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP48121539A
Other languages
Japanese (ja)
Other versions
JPS5321982B2 (OSRAM
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4996645A publication Critical patent/JPS4996645A/ja
Publication of JPS5321982B2 publication Critical patent/JPS5321982B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
JP12153973A 1972-10-30 1973-10-29 Expired JPS5321982B2 (OSRAM)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00302225A US3814925A (en) 1972-10-30 1972-10-30 Dual output adder and method of addition for concurrently forming the differences a{31 b and b{31 a

Publications (2)

Publication Number Publication Date
JPS4996645A true JPS4996645A (OSRAM) 1974-09-12
JPS5321982B2 JPS5321982B2 (OSRAM) 1978-07-06

Family

ID=23166842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12153973A Expired JPS5321982B2 (OSRAM) 1972-10-30 1973-10-29

Country Status (2)

Country Link
US (1) US3814925A (OSRAM)
JP (1) JPS5321982B2 (OSRAM)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4308589A (en) * 1979-11-08 1981-12-29 Honeywell Information Systems Inc. Apparatus for performing the scientific add instruction
US4366548A (en) * 1981-01-02 1982-12-28 Sperry Corporation Adder for exponent arithmetic
US5093775A (en) * 1983-11-07 1992-03-03 Digital Equipment Corporation Microcode control system for digital data processing system
US4639887A (en) * 1984-02-24 1987-01-27 The United States Of America As Represented By The United States Department Of Energy Bifurcated method and apparatus for floating point addition with decreased latency time
CA1257003A (en) * 1985-06-19 1989-07-04 Tadayoshi Enomoto Arithmetic circuit
US4858166A (en) * 1986-09-19 1989-08-15 Performance Semiconductor Corporation Method and structure for performing floating point comparison
JPS6395533A (ja) * 1986-10-09 1988-04-26 Mitsubishi Electric Corp 論理回路
US4811272A (en) * 1987-05-15 1989-03-07 Digital Equipment Corporation Apparatus and method for an extended arithmetic logic unit for expediting selected floating point operations
JPH0776911B2 (ja) * 1988-03-23 1995-08-16 松下電器産業株式会社 浮動小数点演算装置
US4979141A (en) * 1988-09-28 1990-12-18 Data General Corporation Technique for providing a sign/magnitude subtraction operation in a floating point computation unit
JP2606331B2 (ja) * 1988-11-07 1997-04-30 日本電気株式会社 絶対値加減算方法及びその装置
JPH038018A (ja) * 1989-06-06 1991-01-16 Toshiba Corp 符号付き絶対値加減算器
US4999803A (en) * 1989-06-29 1991-03-12 Digital Equipment Corporation Floating point arithmetic system and method
US5075879A (en) * 1989-10-13 1991-12-24 Motorola, Inc. Absolute value decoder
JPH0484317A (ja) * 1990-07-27 1992-03-17 Nec Corp 算術論理演算ユニット
US5278783A (en) * 1992-10-30 1994-01-11 Digital Equipment Corporation Fast area-efficient multi-bit binary adder with low fan-out signals
US5881274A (en) * 1997-07-25 1999-03-09 International Business Machines Corporation Method and apparatus for performing add and rotate as a single instruction within a processor
JP2000155671A (ja) * 1998-11-24 2000-06-06 Mitsubishi Electric Corp 浮動小数点演算装置
US6539413B1 (en) * 2000-03-15 2003-03-25 Agere Systems Inc. Prefix tree adder with efficient sum generation

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2007353C3 (de) * 1970-02-18 1973-11-29 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Vierteiliges Addierwerk

Also Published As

Publication number Publication date
US3814925A (en) 1974-06-04
JPS5321982B2 (OSRAM) 1978-07-06

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