JPH1197289A - Thin-film chip capacitor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film chip capacitor in which the occurrence of leakage currents is suppressed, and a method for manufacturing the capacitor. SOLUTION: A thin-film chip capacitor has a lower electrode thin-film layer 3, a dielectric thin-film layer 4, an upper electrode thin-film layer 5, and a protective thin-film layer 6 which are successively formed in this order on a substrate 2 and bumps 7 for connection. The dielectric thin-film layer 4 is composed at least of two dielectric crystalline thin films 4a and 4b. This capacitor is manufactured by using a method for forming the dielectric thin-film layer 4 by repeating the forming process of the dielectric crystalline thin film 4 by applying a solution, containing the starting material of dielectric crystals to the layer 3 or thin film 4a from which the dielectric crystalline thin film is to be formed and forming a dried gel by drying the solution by the sol-gel method, and then, forming the dielectric crystals by heating the dried gel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a thin film chip capacitor. More specifically, the present invention relates to a thin film chip capacitor in which a dielectric thin film is formed by a sol-gel method (organic metal decomposition (MOD) method).

[0002]

2. Description of the Related Art In recent years, semiconductor devices are required to cope with higher speed, higher frequency, and lower noise. Generally, in order to reduce noise such as simultaneous switching noise, a power supply circuit is provided with a bypass capacitor.

It has long been known that lowering the impedance of a power supply circuit is effective in reducing noise accompanying power supply voltage fluctuation of a semiconductor device, such as simultaneous switching noise. As is well known, the impedance Z of the power supply circuit is given by the following equation.

[0004]

(Equation 1)

[0005] According to this equation, there is a frequency f _c for the impedance Z to the minimum, f _c = (2π (L
C) ^1/2 ) ^-1 . By reducing the wire resistance R of the power supply circuit, but certainly impedance Z can be reduced in the vicinity f _c, in practice, it is required to control below a certain value the impedance at a certain frequency band.
From the relationship between the frequency and the impedance represented by the above formula (1), the frequency band that gives a constant value or less of the impedance in the electrostatic capacity increases that becomes wider, the inductance becomes smaller f _c is the high frequency side It can be seen that moving and, as the wire resistance decreases, the overall impedance decreases. In consideration of the conductor inductance and the capacity of a semiconductor device such as an LSI used, it is desirable that the bypass capacitor of the power supply circuit functions as a broadband noise elimination filter.
_c = 3 to 5f _cl (where f _cl represents the clock frequency of the system), and the impedance Z is 0.05 to
It is often required to control to be about 0.10Ω.

A ceramic capacitor is used as a bypass capacitor in a power supply circuit. Ceramic capacitors use ceramics as a dielectric, and are formed by laminating green sheets of powdered dielectric material (some of these green sheets have conductors of the electrode material printed on them). It is manufactured by firing. Although ceramic capacitors can satisfy the requirements for capacitance, they cannot be reduced in terminal size because soldering or bonding with conductive resin is used for connection to the outside. It is difficult to make the inductance component small enough. Therefore, when a ceramic capacitor is used, the impedance increases particularly in a high-frequency region.

[0007] It is also possible to use a solid electrolyte capacitor as a bypass capacitor. Most solid electrolyte capacitors use TCNQ complex salts, manganese dioxide, polypyrrole, etc. as the electrolyte and aluminum or tantalum as the electrode material. The characteristics of the solid electrolyte capacitor are that while the capacitance can be increased, the shape tends to be large, and it is inferior to the ceramic capacitor in terms of temperature characteristics and heat resistance.

[0008] It is also possible to use a thin-film chip capacitor as a bypass capacitor. A thin film chip capacitor has a laminated structure in which a dielectric thin film layer of metal oxide is inserted between two electrode layers (metal thin film layers) on a substrate, and a surface provided on an upper electrode layer. A solder bump for connecting to an external circuit is formed on the protective layer. Since such a thin film chip capacitor is manufactured using the thin film forming technology used in the manufacture of semiconductor devices, the shape can be reduced, and it is easy to apply to the surface mounting technology often used in semiconductor device mounting. Is the feature. Furthermore, in a thin film chip capacitor, the solder bump for connection to an external circuit can be formed small, so that its inductance component can be reduced, and the use of metal oxide as a dielectric material can realize heat resistance superior to that of a solid electrolyte capacitor. .

In the production of a thin film chip capacitor, a sol-gel method (MOD) is used to form a dielectric thin film layer.
Method) is used. Specifically, a solution (including water for hydrolysis) of a metal alcoholate, which is a starting material of a dielectric thin film material of a metal oxide, is applied on the lower electrode layer formed on the substrate, and the solution is heated to be heated. The decomposition and polymerization reactions are caused to change the solution into a gel state (dry gel) through the sol state of the organometallic oxide, and the dried gel is further heated to form a crystalline inorganic material usable as a dielectric in a capacitor. Change to material (metal oxide).

In the formation of a dielectric thin film by the sol-gel method, after forming a porous gel thin film by calcination, a hydrolyzed sol is applied on the thin film, and calcination is performed again to form a thick dielectric thin film without cracks. The technology obtained is disclosed in Japanese Patent Laid-Open No. 6-1125.
No. 50 publication. The technology described in this publication is
The present invention relates to a dielectric thin film as a piezoelectric material, and a porous gel thin film for re-coating a sol is not completely crystallized by being completely fired, and has essentially no crystal grain boundary. different.

[0011]

As described above, conventional thin film chip capacitors in which a dielectric thin film layer is formed by a sol-gel method are easy to apply to surface mounting technology, and have a solder for connection to an external circuit. While there is an advantage that the inductance component of the bump can be reduced and the heat resistance is superior to that of the solid electrolyte capacitor, the leakage current is relatively large, and there has been a strong demand for improvement in the electrical characteristics of the capacitor.

Accordingly, an object of the present invention is to provide a thin-film chip capacitor which suppresses generation of leakage current and has excellent electrical characteristics. It is also an object of the present invention to provide a method for manufacturing such a thin film chip capacitor.

[0013]

The thin film chip capacitor of the present invention has a laminated structure in which a lower electrode thin film layer, a dielectric thin film layer, an upper electrode thin film layer, and a protective thin film layer are sequentially formed on a substrate. A thin film chip capacitor in which a bump for connection to an external circuit is located on a surface of a protective thin film layer, wherein the dielectric thin film layer is composed of at least two dielectric crystal thin films. .

According to the method of manufacturing a thin film chip capacitor of the present invention, a lower electrode thin film layer, a dielectric thin film layer, an upper electrode thin film layer, and a protective thin film layer are sequentially formed on a substrate, and an external circuit is formed on the surface of the protective thin film layer. A method of manufacturing a thin film chip capacitor by forming a bump for connection to a,
The dielectric thin film layer is formed as a laminated structure of at least two dielectric crystal thin films, and the formation of the laminated structure includes the starting material of the dielectric crystal on the layer or the thin film on which the dielectric crystal thin film is to be formed. The method is characterized in that a step of applying a solution to form a dry gel by a sol-gel method and then heating the dry gel to form a dielectric crystal to form a dielectric crystal thin film is repeated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a thin film chip capacitor according to the present invention will be described. The thin film chip capacitor 1 of the present invention includes a laminate of a lower electrode thin film layer 3, a dielectric thin film layer 4, an upper electrode thin film layer 5, and a protective thin film layer 6 formed on a substrate 2. A bump 7 is provided on the surface. Two of the four bumps 7 shown in this figure communicate with the upper electrode thin film layer 5, and the other two communicate with the lower electrode thin film layer 3. In this figure, four bumps 7 are shown.
Can have any other number of bumps.

As shown in FIG. 2 which is a sectional view taken along the line II-II of FIG. 1, the dielectric thin film layer 4 of the thin film chip capacitor 1 of the present invention comprises a first dielectric crystal thin film 4a and a second dielectric crystal thin film 4a. It is composed of a laminate of the body crystal thin film 4b. One of the two bumps 7 shown in this figure communicates with the upper electrode thin film layer 5 through the contact hole formed in the protective thin film layer 6, and the other bump has the protective thin film layer 6, the upper electrode thin film layer 5, and the dielectric. It communicates with the lower electrode thin film layer 3 through a contact hole formed in the body thin film layer 4.

As the substrate 2 used in the thin-film chip capacitor 1 of the present invention, any substrate on which a thin film can be formed by using a thin-film forming technique used in the manufacture of a semiconductor device can be used. . A typical example is a silicon substrate. The crystal plane orientation and impurity concentration of silicon used as the substrate may be any.

The lower and upper electrode thin film layers 3, 5 can be formed from an appropriate metal material by, for example, a method such as sputtering. Suitable materials for the lower electrode thin film layer 3 are Pt (about 0.3 μm in thickness) and Ir (about 0.3 μm in thickness).
μm), Ru (about 0.3 μm in thickness), Ti (about 0.3 μm in thickness).
1 μm) and Pt (thickness: about 0.3 μm), Ta
(Thickness of about 0.1 μm) and Pt (thickness of about 0.3 μm); Ru (thickness of about 0.3 μm) and RuO ₂ (thickness of about 0.2 μm); Suitable materials for the upper electrode thin film layer 5 are CrW (about 0.1 μm thick) and Cu
(Thickness of about 1.0 μm) and a laminate of CrW (about 0.1 μm), and a laminate of Cr (about 0.1 μm), Cu (about 1.0 μm), and Cr (about 0.1 μm) body,
A laminate of TiN (about 0.1 to 0.2 μm in thickness), Cu (about 1.0 μm in thickness), and Cr (about 0.1 μm in thickness);
A laminate of TiN (about 0.1 to 0.2 μm in thickness), Cu (about 1.0 μm in thickness), and CrW (about 0.1 μm in thickness) (in the latter two laminates including the TiN thin film, the TiN thin film is a dielectric Disposed on the side in contact with the thin film layer).

The dielectric thin film layer 4 comprises a laminate of a first dielectric crystal thin film 4a and a second dielectric crystal thin film 4b. The number of the dielectric crystal thin films constituting the dielectric thin film layer 4 is not limited to two, and the dielectric thin film layer 4 of the thin film chip capacitor of the present invention may be composed of three or more dielectric crystal thin films. The dielectric crystal thin film can be formed, for example, of a material selected from the following dielectric metal oxides.

STO (SrTiO ₃ ) BST ((Ba, Sr) TiO ₃ ) PZT (Pb (Zr, Ti) O ₃ ) PLZT ((Pb, La) (Zr, Ti) O ₃ ) BTO (BaTiO ₃ ) PMN (Pb (Mg _1/3 Nb _2/3 ) O ₃ ) Ta ₂ O ₅

The individual dielectric crystal thin films constituting the dielectric thin film 4 may be formed from the same material or different materials.

Each dielectric crystal thin film is formed from a solution containing a metal alcoholate, which is a starting material of a metal oxide or a metal composite oxide of the material, and water for hydrolysis (this solution generally contains a solvent and a polymerization catalyst). Is applied to the surface of the layer on which the dielectric crystal thin film is to be formed (the lower electrode thin film layer) or the thin film (the already formed dielectric crystal thin film), and a dry gel of metal oxide is formed by a sol-gel method. The dried gel is then heated and crystallized to form. As a method for applying the solution, a spin coating method or a dip coating method can be used. The sol-gel method of making metal oxides from metal alcoholate starting materials is a widely known method and need not be described in detail here. In the following examples, a method for forming the dielectric thin film layer of the present invention by a sol-gel method is described in detail as an example.

A metal alloy which is a starting material of a dielectric crystal thin film
As the colate, any alcohol containing a predetermined metal can be used.
Can be used. As an example, BST ((B
a, Sr) TiO_Three) To form a dielectric crystal thin film
If it does, Ba (OCH _Three)_Two, Sr (OCH_Three)
_TwoAnd Ti (OC_ThreeH₇)_FourUse an alcoholate such as
Can be Solutions containing alcoholate are
It may be prepared by mixing
Solution (alcoholate, water, solvent, catalyst, etc.)
You may use what is marketed. Such a city
As an example of a commercially available solution, High Purity Chemical Research Co., Ltd.
ST-06 (for forming STO dielectric thin film), Symme
Trick's SYM-SR05, SYN-BA05,
SYN-TI05 and the like.
Products sold by Mitsubishi Materials can be used.
You.

The heating for obtaining the desired dielectric crystal thin film from the dried gel of the metal composite oxide formed by the sol-gel method can be performed at a temperature of 600 to 800 ° C. in an oxygen atmosphere or air.

To form the dielectric thin film layer in the present invention, a second dielectric crystal thin film is further formed on the first dielectric crystal thin film formed on the lower electrode thin film layer. The second dielectric crystal thin film can be formed using the same starting material and the same processing step as the first dielectric crystal thin film. The thicknesses of the first and second dielectric crystal thin films can be selected so that the total thickness of both thin films is a thickness necessary for obtaining the predetermined electrical characteristics of the thin film chip capacitor of the present invention. Although three or more dielectric crystal thin films may be formed,
For the purpose of the present invention of suppressing the leakage current of the capacitor, it is sufficient that the dielectric thin film layer is composed of two dielectric crystal thin films. Preferably, the first thin film is formed so as to have a thickness close to a predetermined thickness of the dielectric thin film layer of the capacitor, and the second thin film is formed correspondingly thin. In order to form a thin second film, the concentration of the starting metal alcoholate solution may be changed if necessary. For example, a commercially available metal alcoholate solution (many of which generally has a concentration of a solid component (a component that gels to give a thin film) of about 6 to 8% by weight) is used as it is for forming the first thin film, and For forming the second thin film, a solution obtained by diluting this solution to, for example, about 0.1 to 1.0% by weight can be used. Generally 0.1% by weight
With a solution having a lower concentration, it is difficult to obtain a good dry gel film by the sol-gel method. With a solution having a solid component concentration exceeding 1% by weight, it is difficult to reduce the thickness of the second thin film as desired. Be disadvantaged.

In the present invention, by forming the dielectric thin film layer from at least two dielectric crystal thin films in this way, the leakage current of the thin film chip capacitor can be suppressed. Although this mechanism has not been fully elucidated, it is thought that the gap between the grain boundaries of the dielectric crystal, which is considered to be a path of leakage current, is buried when another crystal thin film is formed on the crystal thin film. Can be As shown in FIG. 3, the dielectric thin film 4 ′ formed by heating and crystallizing the dried gel obtained by the sol-gel method has crystal grain boundaries, and the gaps between the crystal grain boundaries are present. It is understood that 11 is responsible for the leakage current of the capacitor. According to the present invention, when the dielectric thin film layer 4 is formed of two dielectric crystal thin films 4a and 4b as shown in FIG. 4, when another thin film 4b is formed on the lower thin film 4a, this thin film 4b is formed.
It is considered that a part of the material described above at least partially fills the gaps 11 at the crystal grain boundaries of the thin film 4a (this filling is not shown in the drawing), thereby blocking the path of the leakage current. It is also conceivable that the position of the crystal grain boundary of the thin film 4a and the position of the crystal grain boundary (not shown) of the thin film 4b deviate from each other, so that the path of the leakage current may be cut off. .

Furthermore, if the dielectric thin film layer is composed of two crystal thin films, foreign matter (eg, organic matter) larger than the crystal grain boundary
It can also be expected to have an effect of covering defects such as defects and pinholes, thereby contributing to improvement of the electrical characteristics of the thin film chip capacitor. Therefore, particularly when the dip coating method is used, the application of the metal alcoholate solution for forming at least one of the second and subsequent dielectric crystal thin films is performed under a pressure of at least atmospheric pressure, for example, 1013 to 5066 hPa. It is advantageous to work under a pressure of

The protective thin film layer 6 (FIGS. 1 and 2) on the upper electrode thin film layer 5 is made of, for example, a photosensitive material in consideration of conditions such as heat resistance when forming a bump electrode and heat resistance when mounting a thin film chip capacitor. It can be formed from various resin materials such as polyimide resin, non-photosensitive polyimide resin, epoxy resin, and bismaleimide triazine resin.

A bump 7 for connection to an external circuit (FIG. 1,
2) can be formed from any solder. Examples of suitable solder include Pb-Sn solder, In solder, In-S
n solder, In-Pb solder, and the like. Alternatively, gold may be used as the bump material. Bump 7
After placing solder balls of appropriate size in place,
It can be formed by heat treatment and reflow. Alternatively, it may be formed by applying a solder material by a method such as plating, transfer, or vapor deposition and then reflowing.

When the solder bump 7 is formed, after forming a contact hole leading to the upper or lower electrode thin film layer to which the solder bump 7 is connected, a barrier metal thin film layer (see FIGS. (Not shown). The barrier metal thin film layer can be formed by electrolytic plating or electroless plating. Preferably, the barrier metal material is selected according to the bump material used. For example, when the bump material is Pb-Sn solder, the barrier metal thin film layer can be formed from Ni (about 2.0 μm in thickness) and Au (about 0.1 μm in thickness). The bump material is In solder, In-S
In the case of n solder or In-Pb solder, Pt can be used as a barrier metal material, and when the bump material is Au, Pd and Pt can be used as barrier metal materials.

As will be understood from the above description, the thin film chip capacitor of the present invention is used in ordinary semiconductor device production except that the dielectric thin film layer is formed by repeating the sol-gel method. It is manufactured using a thin film forming technique and a bump forming technique. Just as the sol-gel method is well known, such thin film forming techniques and bump forming techniques are widely known and need not be described in detail here. The following examples specifically describe one example of these techniques.

[0032]

Next, the present invention will be further described with reference to examples.
It goes without saying that the invention is in no way limited by these examples.

Example 1 This example describes a thin-film chip capacitor using STO (SrTiO ₃ ) crystals as a dielectric material.

As shown in FIG. 5A, the thickness is 650 μm.
m silicon substrate 21 is thermally oxidized at 1000 ° C. under wet conditions to form an oxide film (not shown) having a thickness of 0.3 μm on the surface of the substrate. .
A 3 μm Pt thin film was deposited, and the Pt thin film was patterned to form a lower electrode thin film layer 22.

Next, on the lower electrode thin film layer 22, a solution containing a metal alcoholate as a starting material of STO (ST-06 of Kojundo Chemical Laboratory Co., Ltd.) is spin-coated,
After forming a coating film having a thickness of μm, the film is dried at 200 ° C. for 30 minutes (this drying may be performed using a digitizer), and then heat-treated at 500 ° C. for 60 minutes in an oxygen atmosphere to form a ST film.
A dry gel of O was formed. A series of operations from application of the metal alcoholate solution to formation of the dried gel was further repeated twice. After the formation of the last (ie, third) dried gel,
Subsequently, a crystallization heat treatment is performed at 650 ° C. in an oxygen atmosphere for 60 minutes.
5 minutes to form a first crystalline thin film 23a (FIG. 5).
(B)).

On this first crystalline thin film 23a, an STO
The solution obtained by diluting the ST-06 for forming a dielectric thin film to reduce the solid content concentration to 0.6% by weight was spin-coated to form a solution.
After forming a coating film of 03 μm, drying at 200 ° C. for 30 minutes, and heating at 500 ° C. for 60 minutes in an oxygen atmosphere, the obtained gel is subsequently heated at 650 ° C. for 60 minutes to crystallize, thereby obtaining a second crystal. The thin film 23b is formed and the dielectric thin film layer 2 is formed.
No. 3 was produced (FIG. 5B).

Next, as shown in FIG. 5C, the formed dielectric crystal thin film 23 was etched to form a contact hole 24 for connecting a lower electrode. 2.5% HF or 2.5% BHF (H with buffer)
F) was used. Subsequently, C constituting the upper electrode thin film layer
rW, Cu, and CrW thin films are formed by sputtering at thicknesses of 0.1 μm, 1.0 μm, and 0.1 μm, respectively.
Patterned by etching, upper electrode thin film layer 25
Was formed. FIG. 5C does not show the three thin films constituting the upper electrode thin film layer 25 for simplicity. In addition, FIG. 5D and FIG.
6A and FIG. 6B, the dielectric crystal thin film layer 2
3, two crystalline thin films 23a and 23b are not shown for the sake of simplicity.

Subsequently, a photosensitive polyimide (PIMELG7613N manufactured by Asahi Kasei Corporation) was applied on the upper electrode thin film layer 25, polymerized by ultraviolet rays, and then thermally cured to form a thin film having a thickness of 5.0 μm. This thin film was patterned by etching to form a protective thin film layer 26 provided with a contact hole 24 'communicating with the lower electrode thin film layer 22 and a contact hole 27 communicating with the upper electrode thin film layer 25 (FIG. 5D).

On the protective thin film layer 26, a 2.0 μm thick N
An i film and an Au film having a thickness of 0.1 μm were sequentially formed by a plating method, and were patterned to form a barrier metal thin film layer 28 serving as a bump underlayer (FIG. 6A). In this figure, the Ni film constituting the barrier metal thin film layer 28 and Au
The membrane is not shown for simplicity.

Next, a 100 μm diameter solder (Pb / Sn = 40/60 wt%) is placed at the position of the contact hole 28.
The ball was placed and heat-treated at 200 ° C. for 60 seconds to cause reflow to form a solder bump 29 (FIG. 6B).

The characteristics of the thin film chip capacitor thus manufactured were measured. The results obtained are shown in FIG. 7 in comparison with the results obtained for a thin-film chip capacitor similarly prepared except that the second dielectric crystal thin film 23b was not formed. The solid line is the result for the capacitor of the example of the present invention, and the broken line is the result for the capacitor for comparison. It can be seen that the leakage current of the capacitor of the present invention is reduced to about 1/3 as compared with the comparative capacitor.

[Embodiment 2] Two S layers as a dielectric thin film layer
Instead of a TO film, two BST ((Ba, Sr) TiO
₃ ) A thin-film chip capacitor was produced in the same manner as in Example 1 except that a film was used. For the formation of the BST film, an alcoholate solution (BST-06) manufactured by Kojundo Chemical Laboratory Co., Ltd. was used under the same conditions as in Example 1.

The characteristics of the manufactured thin film chip capacitor were measured. The results obtained are shown in FIG. 8 in comparison with the results obtained for a similarly fabricated thin film chip capacitor except that the second dielectric crystal thin film was not formed. Also in this figure, the solid line is the result for the capacitor of the example of the present invention, and the broken line is the result for the capacitor for comparison. Also in this case, the leakage current of the capacitor of the present invention was reduced to about 1/3 as compared with the comparative capacitor.

[0044]

As described above, according to the present invention,
It is possible to provide a thin-film chip capacitor excellent in electric characteristics, in which a leakage current flowing through a crystal grain boundary of a dielectric layer is largely suppressed.

[Brief description of the drawings]

FIG. 1 is a perspective view illustrating a thin film chip capacitor of the present invention.

FIG. 2 is a sectional view taken along line II-II of FIG.

FIG. 3 is a diagram illustrating a dielectric crystal thin film formed by a sol-gel method.

FIG. 4 is a diagram illustrating a dielectric thin film layer in the thin film chip capacitor of the present invention.

FIG. 5 is a diagram illustrating the first half of the manufacturing process of the thin-film chip capacitor of Example 1.

FIG. 6 is a diagram illustrating the latter half of the manufacturing process of the thin-film chip capacitor of Example 1.

FIG. 7 is a graph illustrating characteristics obtained for the thin-film chip capacitor of Example 1.

FIG. 8 is a graph illustrating characteristics obtained for the thin film chip capacitor of Example 2.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Thin film chip capacitor 2 ... Substrate 3 ... Lower electrode thin film layer 4 ... Dielectric thin film layer 4a, 4b ... Dielectric crystal thin film 5 ... Upper electrode thin film layer 6 ... Protective thin film layer 7 ... Bump 11 ... Gap between crystal grain boundaries 21 ... Silicon substrate 22 ... Lower electrode thin film layer 23 ... Dielectric thin film layer 24, 24 ', 27 ... Contact hole 25 ... Upper electrode thin film layer 26 ... Protective thin film layer 28 ... Barrier metal thin film layer 29 ... Solder bump

Claims (12)

[Claims] 1. A laminated structure in which a lower electrode thin film layer, a dielectric thin film layer, an upper electrode thin film layer, and a protective thin film layer are sequentially formed on a substrate, and a surface of the protective thin film layer is connected to an external circuit. A thin film chip capacitor on which bumps are located, wherein the dielectric thin film layer is composed of at least two dielectric crystal thin films. 2. The method according to claim 1, wherein the dielectric crystal thin film is STO, BST,
PZT, PLZT, BTO, are formed in the crystals of PMN or Ta ₂ O _5, thin film chip capacitor of claim 1, wherein. 3. A lower electrode thin film layer, a dielectric thin film layer, an upper electrode thin film layer, and a protective thin film layer are sequentially formed on a substrate, and bumps for connection to an external circuit are formed on the surface of the protective thin film layer. A method of manufacturing a thin film chip capacitor by forming the dielectric thin film layer as a laminated structure of at least two dielectric crystal thin films, and forming the laminated structure by forming the dielectric crystal thin film. A solution containing a starting material of a dielectric crystal is applied on a layer or a thin film to be formed to form a dry gel by a sol-gel method, and then the dried gel is heated to form a dielectric crystal, thereby forming a dielectric crystal thin film. A method for producing a thin film chip capacitor, characterized by performing the step of forming a thin film chip capacitor. 4. The method according to claim 1, wherein the dielectric crystal thin film is formed of STO, BST,
PZT, PLZT, BTO, formed in the crystal of PMN or Ta ₂ O _5, The method of claim 3. 5. The method according to claim 3, wherein a solution of a metal alcoholate is used as a starting material for the dielectric crystals. 6. The method according to claim 5, wherein the application of the solution of the metal alcoholate is performed by spin coating or dip coating. 7. After forming a first dielectric crystal thin film on the lower electrode thin film layer, dilute the metal alcoholate solution used for forming the first dielectric crystal thin film with the first dielectric crystal thin film. 7. The method of claim 6, wherein the method is applied on a body crystal thin film to form a second dielectric crystal thin film. 8. The metal alcoholate solution used for forming said second dielectric crystal thin film has a solid component concentration of 0.1 to 0.1.
8. The method according to claim 7, wherein the solution used for forming the first dielectric crystal thin film is diluted to 1.0% by weight. 9. Forming one or more dielectric crystal thin films on the second dielectric crystal thin film using the same solution used for forming the second dielectric crystal thin film, 9. A method according to claim 7 or claim 8. 10. The method according to claim 8, wherein the second dielectric crystal thin film is formed by dip coating under pressure. 11. The method according to claim 8, wherein at least one of the second dielectric crystal thin film and the dielectric crystal thin film formed thereon is formed by dip coating under pressure. 12. The dip coat according to claim 10, wherein
The method according to claim 10, wherein the method is performed under a pressure of 66 hPa.