JPH1187528A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the electrostatic breakdown voltage of a parasitic insulated gate type field effect transistor with a simple structure in a semiconductor device having an input gate protective circuit formed of the transistor at a position near a bonding metal wire. SOLUTION: In this semiconductor device comprising an input gate protective circuit 40 connected to an input gate circuit formed of an insulated gate type field effect semiconductor element, the circuit 40 is formed of a parasitic insulated gate type field effect semiconductor element having a drain diffused layer 43 connected to a bonding metal wiring 10 and a source diffused layer 41 connected to a ground metal wiring 50 and formed between the wiring 10 and the wiring 50, flat surface shapes of the layers 43 and 41 are formed into a bent shape, formed continuously in two or more directions of the wiring 10, and the shape of the bent part is formed in a curve.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device provided with an input gate protection circuit connected to an input gate circuit composed of an insulated gate field effect semiconductor device.

[0002]

2. Description of the Related Art An insulated gate field effect semiconductor device is
The input impedance of the input transistor is extremely high,
Moreover, since the thickness of the insulating film is small, only a low withstand voltage can be obtained. Therefore, there is a problem that the insulating film of the gate portion is easily destroyed by static electricity generated by friction or the like. Therefore, in a semiconductor device in which an input gate circuit is formed using such an insulated gate type field effect type semiconductor element, a protection circuit is usually provided on the input gate as a measure to prevent the insulation film breakdown of the insulated gate type field effect type semiconductor element. Is connected.

Various circuits having various configurations have been put into practical use as an input gate protection circuit.
In order to increase the electrostatic breakdown voltage, a parasitic insulated gate field effect type semiconductor element having one electrode grounded is formed near a bonding metal wiring in order to increase the electrostatic breakdown voltage. It has been proposed to release high-voltage static electricity applied to the bonding metal wiring.

Referring to FIG. 6, an outline of the configuration of a parasitic insulated gate field effect type semiconductor element portion of such a circuit will be described. The parasitic insulated gate field effect transistor 40 includes a bonding metal wiring 10 provided on a semiconductor substrate, a ground metal wiring 50, a source diffusion layer 41 provided below these two wirings, and a bonding metal wiring. 10, an ohmic contact 42 connecting the ground metal wiring 50 to the source diffusion layer 41, an ohmic contact 44 connecting the bonding metal wiring 10 to the drain diffusion layer 43, A gate 45 is provided between the diffusion layer 41 and the drain diffusion layer 43 below the bonding metal wiring 10.

However, the parasitic insulated gate type field effect transistor having such a shape is not
In such a case, there is a problem that thermal destruction occurs due to concentration of an electric field, and as a result, electrostatic breakdown voltage of the input gate protection circuit is reduced.

[0006]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a parasitic insulating gate type field effect transistor used as an input gate protection circuit near a bonding metal wiring. It is an object of the present invention to improve the electrostatic breakdown withstand voltage of a parasitic insulated gate field effect transistor with a simple structure in a semiconductor device in which is formed.

[0007]

According to the present invention, there is provided a semiconductor device having an input gate protection circuit connected to an input gate circuit comprising an insulated gate type field effect semiconductor element. An input gate protection circuit includes a drain diffusion layer connected to a bonding metal wiring, a source diffusion layer connected to a ground metal wiring, and a parasitic insulating gate type electric field formed between the bonding metal wiring and the ground metal wiring. The drain diffusion layer and the source diffusion layer are formed of an effect-type semiconductor element, and the planar shape of the drain diffusion layer and the source diffusion layer is a bent shape continuously formed in two or more directions of the bonding metal wiring, and the shape of the bent portion is a curve. .

Further, according to the present invention, in the semiconductor device described above, the parasitic insulating gate type field effect type semiconductor element surrounds the entire periphery of the bonding metal wiring.
Further, according to the present invention, in the above-described semiconductor device, the metal wiring connection portions of the drain diffusion layer and the source diffusion layer of the parasitic insulated gate field effect semiconductor element may have a planar shape continuous in two or more directions of the bonding metal wiring. In addition to the formed bent shape, the shape of the bent portion was all curved.

[0009]

Since the input gate protection circuit is formed by using the parasitic insulating gate type field effect type semiconductor device having the above configuration, it is possible to suppress, for example, thermal destruction occurring at the point A in FIG. As a result, an input gate protection circuit having a high electrostatic breakdown voltage can be obtained. Further, the planar shape of the drain diffusion layer and the source diffusion layer of the parasitic insulated gate type field effect type semiconductor device is a bent shape formed continuously in two directions of the bonding metal wiring, and the shape of the bent portion is curved. Therefore, the electric field does not concentrate on the end of the drain diffusion layer, and thermal destruction due to the electric field concentration can be suppressed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The outline of the configuration of an input gate protection circuit used in the present invention will be described with reference to FIG. The input gate protection circuit includes a bonding metal wiring 10, a ground metal wiring 50 of a semiconductor device, and a parasitic insulating gate type field effect transistor 40 formed between both electrodes.

A parasitic insulated gate field effect transistor 40 formed on a semiconductor substrate is disposed below the bonding metal wiring 10 and connected to the wiring 10 through an opening in an insulating layer provided on the substrate. And a source diffusion layer 41 disposed below the bonding metal wiring 10 and the ground metal wiring 50 and connected to the ground metal wiring 50 through an opening in an insulating layer provided on the substrate. And bonding metal wiring 10 provided between drain diffusion layer 43 and source diffusion layer 41.
And a gate 45 formed below the gate.
On the source diffusion layer 41, the diffusion layer is
Wiring connection part (ohmic contact) 4 to be connected to
2 is provided, and on the drain diffusion layer 43, a metal wiring connection portion (ohmic contact) 44 for connecting the diffusion layer to the bonding metal wiring 10 is provided.

Source diffusion layer 41 and drain diffusion layer 4
3 is a plan view of the bonding metal wiring 1.
In addition to being formed in a bent shape continuous in two directions of 0, the outside of the bent portion of the diffusion layer located inside is formed in an arc shape in which the electric field is not concentrated. Each of the metal wiring connecting portions 42 and 44 has a planar shape formed continuously in two directions of the bonding metal wiring 10 and a bent portion of the metal wiring connecting portion located inside is formed in an arc shape. is there.

With this configuration, it is possible to suppress the thermal destruction due to the electric field concentration occurring at the end portion such as the point A in FIG. 6, and as a result, to protect the input gate with a high electrostatic breakdown voltage. It can be a circuit.

In the above description, an example was described in which the shape of the bent portion of the diffusion layer and the metal wiring connecting portion was formed in an arc shape.
It may be a relaxation curve in which the curvature decreases from both end portions in contact with the straight line portion to the middle portion, or a curve (bent line) composed of a collection of two or more obtuse angles.

The outline of the configuration of a semiconductor device provided with an input gate circuit using the input gate protection circuit according to the present invention will be described with reference to FIG. In this semiconductor device, a bonding metal wiring 10 and an input gate circuit 2 are formed on a semiconductor substrate.
0, a polycrystalline silicon resistor 30, a parasitic insulated gate field effect transistor 40, and a ground metal wiring 50.

The bonding wire connecting electrode 10 is formed of a metal such as aluminum, and a thin wire (not shown) for inputting a signal is connected by welding.

The input gate circuit 20 comprises, for example, three insulated gate field effect transistors and a resistor. That is, the input gate circuit 20 includes an n-type diffusion layer provided on a semiconductor substrate, a gate 21 made of polycrystalline silicon formed on the n-type diffusion layer via an insulating layer, and a resistor 22 similarly connected to the gate electrode. Is formed, and a ground metal wiring 50 is further formed thereon via an insulating layer. The three insulated gate field effect transistors are respectively connected in parallel, the drains are all connected to a protection resistor 30 made of polycrystalline silicon via a connection conductor 24, and the output terminal 26 is connected via an output conductor 25. It is connected to the. The sources of these field effect transistors are all connected to the ground metal wiring 50. The gates of these field effect transistors are all connected to a ground metal wiring 50 via a ground resistor 22 formed of polycrystalline silicon.

The connection conductor 24 and the output conductor 25 form an ohmic contact 23 in the drain region through an opening provided in the insulating layer. Further, the output conductor 25
Has formed an ohmic contact 23 through an opening provided in an insulating layer at an output terminal 26 obtained as polycrystalline silicon.

The ground metal wiring 50 is provided on the source regions of the three insulated gate field effect transistors, and forms an ohmic contact 23 in the source region through an opening provided in the insulating layer.

The polycrystalline silicon resistor 30 is formed by providing a polycrystalline silicon layer on a semiconductor substrate, and connects between the bonding metal wiring 10 and the connection conductor 24 of the input gate circuit 20.

Parasitic insulated gate field effect transistor 4
0 is a source diffusion layer 41, an ohmic contact 42 connecting the source diffusion layer 41 and the ground metal wiring 50,
A drain diffusion layer 43 and an ohmic contact 44 connecting the drain diffusion layer 43 to the bonding metal wiring 10 are provided below the bonding metal wiring 10 and the ground metal wiring 50. In the semiconductor element 40, a portion located below the bonding metal interconnect 10 between the source diffusion layer 41 and the drain diffusion layer 43 functions as a gate 45.

In this embodiment, the drain diffusion layer 43
Further, the planar shape of the source diffusion layer 41 is formed continuously on three sides of the bonding metal wiring 10.

The circuit configuration of the input gate circuit will be described with reference to FIG. The input gate circuit 20 is configured by connecting three insulated gate field effect transistors G ₁ , G ₂ , G ₃ in parallel and connecting all gates to a ground metal wiring 50 via a ground resistor 22. You. The sources S of the insulated gate field effect transistors G ₁ , G ₂ , G ₃ are:
The drain D is connected to the output Vout, and is connected to the ground metal wiring 50.
0 is connected to input Vin. Insulated gate field effect transistor G ₄ are a parasitic insulated gate field effect transistor 40 connected between the input Vin and the polycrystalline silicon resistor 30, the gate 45 and drain 43 is connected to the input Vin, the source 41 It is connected to the ground metal wiring 50.

With this configuration, when the input is extremely large, the input gate protection circuit 40 conducts and bypasses an excessive input signal, so that the input gate circuit 20 is protected.

Another specific configuration of the input gate protection circuit according to the present invention will be described with reference to FIG. In this embodiment, the source diffusion layer 41 is connected to the bonding metal wiring 10.
Is closed. Similarly, the drain diffusion layer 43 also has a bent portion with a curved shape and a closed shape. In this embodiment,
Although the metal wiring connection portion 44 of the drain diffusion layer 43 has a divided shape, the metal wiring connection portion 4 of the drain diffusion layer 43 is formed.
There is no problem even if 4 is formed in a continuous shape. Further, there is no problem even if the metal wiring connection portion 43 of the source diffusion layer 41 is formed in a divided shape or a continuous substantially closed shape.

Another specific configuration of the input gate protection circuit according to the present invention will be described with reference to FIG. In this embodiment, the drain diffusion layer 43 and the source diffusion layer 41
In this example, the metal wiring connection portion 44 of the drain diffusion layer 43 is also formed in a shape (U-shape) that is continuous in three directions.

Both of the input gate protection circuits shown in FIGS. 4 and 5 are similar to FIG. 2, for example, by arranging two insulated gate type field effect type semiconductor elements in parallel, thereby making the entire input gate protection circuit. Can be improved in electrostatic breakdown voltage.

[0028]

As described above, in the semiconductor device provided with the input gate protection circuit according to the present invention, the electrostatic breakdown withstand voltage can be improved by suppressing the thermal breakdown of the parasitic insulated gate type field effect semiconductor element. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram conceptually showing a planar shape of a parasitic insulated gate field effect transistor of an input gate protection circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor device using an input gate protection circuit according to the present invention.

FIG. 3 is a circuit diagram showing an input gate protection circuit according to the present invention and a circuit configuration of an input gate circuit to which the protection circuit is applied;

FIG. 4 is a diagram showing another configuration of a semiconductor device using the input gate protection circuit according to the present invention.

FIG. 5 is a diagram showing still another configuration of the semiconductor device using the input gate protection circuit according to the present invention.

FIG. 6 is a diagram conceptually showing a planar shape of a parasitic insulated gate field effect transistor of a conventional input gate protection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Metal wiring for bonding, 20 Input gate protection circuit, 21 Gate, 22 Grounding resistance, 23
Ohmic contacts, 24 connection conductors, 25 output conductors, 26 output terminals, 30 polycrystalline silicon resistors, 40 parasitic insulated gate field effect transistors,
41 source diffusion layer, 42 connection part of the source diffusion layer with the metal wiring, 43 drain diffusion layer, 44 connection part of the drain diffusion layer with the metal wiring, 45 gate,
50 Ground metal wiring.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiro Okutsu 2274 Hongo, Ebina-shi, Kanagawa Prefecture Inside Fuji Xerox Co., Ltd. (72) Inventor Kunihito Sato 2274 Hongo, Ebina-shi, Kanagawa Prefecture Inside Fuji Xerox Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor device having an input gate protection circuit connected to an input gate circuit composed of an insulated gate field effect semiconductor element, wherein the input gate protection circuit is connected to a drain diffusion layer and a metal wiring for bonding. Connecting the source diffusion layer to a ground metal wiring, comprising a parasitic insulating gate type field effect type semiconductor element formed between the bonding metal wiring and the ground metal wiring, wherein the drain diffusion layer and the source diffusion layer A semiconductor device having a bent shape formed continuously in at least two directions of the bonding metal wiring, and a bent portion having a curved shape. 2. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein a parasitic insulated gate field-effect semiconductor element entirely surrounds a metal wiring for bonding. 3. The semiconductor device according to claim 1, wherein
The metal wiring connection portions of the drain diffusion layer and the source diffusion layer of the parasitic insulated gate type field effect type semiconductor device have a planar shape formed by continuously forming the metal wiring for bonding in two or more directions, and a bent shape. A semiconductor device, characterized in that all parts have a curved shape.