JPH1187527A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an input gate protective circuit having an electrostatic breakdown voltage which is equivalent to a linear polycrystalline silicon resistor, while suppressing an increase in a region for disposing the protective circuit by reducing restrictions with respect to the region. SOLUTION: In the semiconductor device utilizing a polycrystalline silicon resistor 30 used for part of an input gate protective circuit itself or the input gate protective circuit to be connected to an input gate circuit which uses an insulated gate type field effect semiconductor element, a flat surface shape of the resistor 30 is formed into a zigzag shape, and all the insides of its corners are formed as curves or with obtuse angles. Preferably, the respective insides of the corners in the zigzag part of the flat surface shape of the inside of the resistor is to have a circular arc having a curvature with a radius of 20 μm or more, or an obtuse angle approximating the arc. A width of the resistor is 10 μm or more.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device equipped with a gate protection circuit including an insulated gate field effect semiconductor element.

[0002]

2. Description of the Related Art In a semiconductor device using an insulated gate type field effect type semiconductor element as an input gate circuit, an input transistor comprising the insulated gate type field effect type semiconductor element has an extremely high input impedance and furthermore has an insulated gate type field effect type. Since the thickness of the insulating film of the mold semiconductor element is small, the withstand voltage is low. The insulated gate field effect type semiconductor device has a problem that the insulating film in the gate portion is easily broken by static electricity generated by friction or the like, and the function as the device cannot be exhibited. Therefore, as a countermeasure for preventing such an insulating gate type field effect type semiconductor element from breaking down the insulating film, a method of connecting a protection circuit to the input gate is usually adopted.

As such an input gate protection circuit,
Although various circuit configurations have been put to practical use, many input gate protection circuits use resistors in the input gate protection circuit itself or a part thereof. With this resistor, when a high voltage is applied, the voltage application to the gate is delayed by the CR time constant, or the voltage application to the gate insulating film is suppressed by voltage division. In recent years, as a method of forming such a resistor, generally, a polycrystalline silicon resistor that can be formed simultaneously with a semiconductor element is used as a resistor for an input gate protection circuit.

Here, the electrostatic breakdown voltage of such a circuit includes the strength of the input gate protection circuit itself against a high voltage, and the input gate protection circuit, not the gate insulating film to be protected, often breaks down. The challenge is to do.

[0005] Since the polycrystalline silicon resistor has a mode in which the applied voltage becomes a heating resistor and is blown by a certain current, the input gate protection using the polycrystalline silicon resistor is performed. The electrostatic breakdown voltage of a circuit is often determined by the withstand voltage of the polycrystalline silicon resistor itself. For this reason, it has been necessary to increase the breakdown voltage of the polycrystalline silicon resistor.

Here, the withstand voltage of the polycrystalline silicon resistor is determined by the thickness and the sheet resistance determined by process restrictions.
It shows different values depending on the shape.

As an example of such a protection circuit using a polycrystalline silicon resistor, there is a resistance circuit disclosed in Japanese Patent Application Laid-Open No. 56-2664. In this example, when the resistance made of polycrystalline silicon is bent, local heating occurs due to the concentration of the applied current at the bent portion, and the polycrystalline silicon melts at this portion. Therefore, as shown in FIG. The withstand voltage is increased by making the shape of a straight line.
In FIG. 4, after forming a resistor 30 made of polycrystalline silicon on a substrate, forming an insulating layer having a hole for forming a contact thereon, a metal electrode 10 for connecting a bonding thin wire as an input terminal and a connection. The conductor 24 is formed. The connection conductor 24 for connection to the electrode 10 and the input gate and the resistor 30 are connected by an ohmic contact 23 formed in the opening.

In the configuration of the above protection circuit, in order to set the resistance value of the polycrystalline silicon resistor 30 to a desired value, the protection circuit arrangement area must be large. For example, a sheet resistance of 30 ohm / sq. In order to produce a 300 ohm resistor from the above polycrystalline silicon, it is necessary to form a polycrystalline silicon resistor having a width of 10 μm and a length of 100 μm. Therefore, for example, when the polycrystalline silicon resistors are arranged in the direction in which the bonding metal wirings are arranged, the distance between adjacent bonding metal wirings is at least 100 μm.
More than necessary.

As described above, when the above-mentioned shape is adopted as the resistance of the protection circuit, in order to obtain a desired resistance value, the linear region of the polycrystalline silicon resistor 30 to be disposed must be long, and the input gate There is a problem that the arrangement area of the protection circuit is restricted.

In order to solve such a problem, as shown in FIG. 5, it is conceivable to reduce the distance between the electrode 10 and the ohmic contact 23 provided on the connection conductor 24 by meandering the polycrystalline silicon resistor. . However,
When the polycrystalline silicon resistor 30 having such a shape is used, the current path is usually the shortest distance, and therefore, becomes a path indicated by the curve I with an arrow, and the current is concentrated on the bent portion 31 to locally generate heat. As a result, there is a problem that the vicinity of the bent portion 31 is disconnected or deteriorated.

[0011]

SUMMARY OF THE INVENTION The present invention relates to an input gate protection circuit connected to an input gate circuit using an insulated gate type field effect semiconductor device or a polycrystalline silicon resistor as a part of the input gate protection circuit. In the semiconductor device being used, the input gate protection circuit having the same electrostatic breakdown voltage as a linear polycrystalline silicon resistor while reducing the restriction on the area where the input gate protection circuit is arranged and suppressing the increase in the area. Get the circuit.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an input gate protection circuit connected to an input gate circuit using an insulated gate type field effect type semiconductor device or an input gate protection circuit. In a semiconductor device partially using a polycrystalline silicon resistor, the planar shape of the polycrystalline silicon resistor is formed in a meandering shape, and all of the insides of the corners are curved or obtuse. Also, the present invention
In the above-described semiconductor device, the inside of the corner of the meandering portion of the planar shape of the polycrystalline silicon resistor is all formed into an arc having a radius of curvature of 20 μm or more or an obtuse angle close to the arc. Further, according to the present invention, in the above semiconductor device, the width of the polycrystalline silicon resistor is set to 10 μm or more.

[0013]

As described above, since the plane shape of the polycrystalline silicon resistor is formed in a meandering shape, and all the insides of the corners are formed with a curve or an obtuse angle, it is possible to prevent current from being concentrated at the corners. In addition, it is possible to prevent disconnection and deterioration of the polycrystalline silicon resistance, and to obtain an electrostatic breakdown voltage equivalent to that of a linear polycrystalline silicon resistance while suppressing an increase in the area where the resistance is disposed. .

Since the plane shape of the polycrystalline silicon resistor is formed in a meandering shape, and all the insides of the corners are curved or obtuse, the minimum distance between adjacent metal wires for bonding is reduced to less than half of the conventional one. And an electrostatic breakdown voltage equivalent to that of a linear polycrystalline silicon resistor can be obtained.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described with reference to FIG. FIG. 1 is an enlarged view of an input gate protection circuit portion of an insulated gate field effect semiconductor device. In the semiconductor device according to the present invention, a resistor 30 made of polycrystalline silicon is formed on a semiconductor substrate, an insulating layer having a hole for forming a contact formed thereon is formed thereon, and then a bonding thin wire for an input terminal is formed. A connection conductor 24 connecting the metal electrode 10 and the input gate is formed. The electrode 10, the connection conductor 24, and the resistor 30 are connected by an ohmic contact 23 formed in the opening. Further, in this embodiment, the polycrystalline silicon resistor 30 has a meandering planar shape, and the inner corner of the meandering portion has an arc.

The width of the polycrystalline silicon resistor 30 is at least 10 μm and the curvature of the corner is at least a radius of 20 μm.
μm. By forming the shape of the polycrystalline silicon resistor 30 in a meandering shape as described above, and by forming the inside of the corner in an arc shape, the current path I does not concentrate on the corner, and disconnection of the resistor and disconnection of the resistor are prevented. Performance degradation can be eliminated.

An example of a semiconductor device having an input gate protection circuit according to the present invention will be described with reference to FIG. In this semiconductor device, a bonding fine wire connecting metal electrode 10, an input gate circuit 20, a polycrystalline silicon resistor 30, and a parasitic insulating gate type field effect type semiconductor element 4 are formed on a semiconductor substrate.
0 and a ground electrode 50 are formed.

The bonding thin wire connection electrode 10 is formed of a metal such as aluminum, and a thin wire (not shown) for inputting a signal is connected by welding.

The input gate circuit 20 comprises, for example, three insulated gate field effect transistors and a resistor. That is, in the input gate circuit 20, an n-type diffusion layer is provided on a semiconductor substrate, a gate 21 made of polycrystalline silicon is formed thereon via an insulating layer, and a resistor 22 similarly connected to a gate electrode is formed. In addition, a ground electrode 50 is further formed thereon via an insulating layer. The three insulated gate field effect transistors are respectively connected in parallel, the drains are all connected to a protection resistor 30 made of polycrystalline silicon via a connection conductor 24, and the output terminal 26 is connected via an output conductor 25. It is connected to the. The sources of these field effect transistors are all connected to the ground electrode 50. The gates of these field effect transistors are all connected to a ground electrode 50 via a ground resistor 22 formed of polycrystalline silicon.

The connection conductor 24 and the output conductor 25 form an ohmic contact 23 in the drain region through an opening provided in the insulating layer. Further, the output conductor 25
Has formed an ohmic contact 23 through an opening provided in an insulating layer at an output terminal 26 obtained as polycrystalline silicon.

The ground electrode 50 has three insulated gates provided on the source region of the multi-field effect transistor.
An ohmic contact 23 is formed in the source region through an opening provided in the insulating layer.

The polycrystalline silicon resistor 30 is formed by providing a polycrystalline silicon layer on a semiconductor substrate, and connects between the bonding thin wire connection electrode 10 and the connection conductor 24 of the input gate circuit 20.

Parasitic insulated gate field effect semiconductor device 40
Are the source region 41, the source region 41 and the ground electrode 5
0, a drain region 43, and an ohmic contact 44 connecting the drain region 43 and the electrode 10. The ohmic contact 42 connects the drain region 43 to the electrode 10, and is provided below the bonding thin wire connecting metal electrode 10 and the ground electrode 50. . In the semiconductor element 40, the electrode 10 functions as a gate.

According to this embodiment, the planar shape of the polycrystalline silicon resistor 30 is formed in a meandering shape, and all the inner corners are constituted by arcs. Here, for example, the polycrystalline silicon resistor 30 has a width of 10 μm, for example.
And an arc having a curvature of a part of a straight line and a radius of 25 μm. As about 90
A resistance of 0 ohm is formed. Here, the metal electrode 1
The distance between the connection 11 between the zero and the polysilicon resistor 30 and the connection 23 between the input gate protection circuit 20 and the polysilicon resistor 30 is about 90 μm. In this embodiment, as the input gate protection circuit 20, for example, two insulated gate field effect semiconductor elements are arranged in parallel to improve the electrostatic breakdown voltage of the entire input gate protection circuit.

Referring to FIG. 3, another embodiment of the polycrystalline silicon resistor 30 in the semiconductor device according to the present invention will be described. This embodiment is characterized in that the corners of the polycrystalline silicon resistor 30 are constituted by a combination of two obtuse angles 32, as compared with the embodiment shown in FIG. Even when the polycrystalline silicon resistor 30 is formed in this shape, it is possible to prevent the current path from being concentrated at the corners as in the embodiment shown in FIG. And deterioration of performance can be prevented.

In the above description, the polycrystalline silicon resistor 30
Although the example in which the planar shape of the arc is formed from an arc or an obtuse angle is shown, the planar shape inside the corner is formed as a relaxation curve in which the curvature gradually decreases from both ends in contact with the straight line to the intermediate portion, so that the current path can be reduced. The shape can be very close.

[0027]

As described above, in the semiconductor device according to the present invention, the input gate protection circuit can be provided without increasing the distance between the bonding metal wirings, and the area in which the input gate protection circuit is arranged is limited. Thus, the input gate protection circuit or the polycrystalline silicon resistor used as a part of the input gate protection circuit can be provided with a layout area that gives a sufficient electrostatic breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an enlarged part of an input gate protection circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor device using the input gate protection circuit shown in FIG.

FIG. 3 is an enlarged configuration diagram showing a part of an input gate protection circuit according to another embodiment of the present invention.

FIG. 4 is a diagram showing a planar shape of a polycrystalline silicon resistor of a conventional input gate protection circuit.

FIG. 5 is a diagram showing another planar shape of a polycrystalline silicon resistor of a conventional input gate protection circuit.

[Explanation of symbols]

10 metal electrode for bonding, 11 ohmic contact, 20 input gate circuit, 21 gate,
22 resistance, 23 ohmic contact, 24
Connection conductor, 25 output conductor, 26 output terminal,
Reference Signs List 30 polycrystalline silicon resistor, 40 parasitic insulated gate field effect transistor, 41 source region, 42
Ohmic contact, 43 drain region, 44
Ohmic contact, 50 ground electrode.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshihiro Okutsu 2274 Hongo, Ebina-shi, Kanagawa Prefecture Inside Fuji Xerox Co., Ltd. (72) Inventor Kunihito Sato 2274 Hongo, Ebina-shi, Kanagawa Prefecture Inside Fuji Xerox Co., Ltd.

Claims (3)

[Claims] An input gate protection circuit connected to an input gate circuit using an insulated gate field effect semiconductor element or a semiconductor device using a polycrystalline silicon resistor for a part of the input gate protection circuit. A semiconductor device, characterized in that the planar shape of the polycrystalline silicon resistor has a meandering shape, and that all inside corners are curved or obtuse. 2. The semiconductor device according to claim 1, wherein
A semiconductor device characterized in that the inside of the corner of the meandering portion of the planar shape of the polycrystalline silicon resistor is an arc having a radius of curvature of 20 μm or more or an obtuse angle close to the arc. 3. The semiconductor device according to claim 2, wherein
A semiconductor device wherein the width of a polycrystalline silicon resistor is 10 μm or more.