JPH04267340A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make the area of a semiconductor integrated circuit small by forming a part or the whole of the field plate electrode of a transistor from a resistive thin film. CONSTITUTION:In place of a metal electrode of aluminum, etc., a silicon- chromium thin-film resistance 111 is formed into an annular shape as field plate electrode in the insulating part of a base diffusion layer 105. An emitter electrode 106 and base electrode 109 formed of aluminum are in ohmic contact with each other in a predetermined part. Therefore, the value of a resistance connected between the emitter and base is the resistance value of a parallel connection of the right-side and left-side halves of the annular silicon-chromium thin-film resistance 111. An NPN transistor constituted in this manner neither requires any area for resistance nor lowers breakdown strength because there is no gap between field plate electrodes.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device using a thin film resistor as a resistance element.

0002

2. Description of the Related Art The prior art will be explained with reference to the drawings. 5 and 6 are a plan view and a cross-sectional view of a high voltage NPN transistor according to the prior art. As an element isolation method,
Although a dielectric separation method often used in high-voltage semiconductor integrated circuit devices is given as an example, other separation methods may be used as this is not a problem here. When a positive voltage is applied to the collector electrode 302 and a negative voltage is applied to the emitter field plate electrode 306 or the base field plate electrode 309 of the NPN transistor, a depletion layer 315 is generated surrounding the base diffusion layer 305 as shown in FIG. The depletion layer 315 is the emitter field plate electrode 30
6 and the base field plate electrode 309, the electric field strength within the depletion layer is weakened, and a high breakdown voltage can be achieved. The emitter field plate electrode 306 and the base field plate electrode 309 are usually formed of metal electrodes such as aluminum. In addition, in order to absorb leakage current between the collector and emitter or to prevent malfunctions due to noise, etc., wires 316a and 316b are drawn out from the emitter field plate electrode 306 and base field plate electrode 309, respectively, and a silicon chrome thin film resistor 311 is connected between the emitter and the base. are doing. Figure 5
Although the silicon-chromium thin film resistor 311 is formed on the single-crystal silicon island 301b, it does not necessarily need to be formed on the single-crystal silicon island, and may be formed on a flat place.

0003

[Problems to be Solved by the Invention] In this conventional semiconductor integrated circuit device, an area other than the area of the transistor is required to place a resistor connected between the emitter and base of the transistor, and the area of the entire semiconductor integrated circuit device is reduced. It had the disadvantage of being large.

[0004] Also, the emitter field plate electrode 30
Since the field plate gap 317 exists between the base field plate electrode 9 and the base field plate electrode, the depletion layer 315 does not extend sufficiently in the gap 317, resulting in a decrease in breakdown voltage. FIG. 7 shows an example of the relationship between the gap 317 and the breakdown voltage of the transistor. gap 317 to 1
If it is 0 μm or less, there will be no drop in withstand voltage, but if the gap is 3
If the width of the field plate 17 is made narrower, the possibility of short circuit between the field plate electrodes increases, resulting in a problem of lower yield.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit device of the present invention is a semiconductor in which a plurality of circuit elements are formed on the main surface of a semiconductor substrate by a selective diffusion method, and electrodes of the circuit elements are connected by wiring. In an integrated circuit device, at least a portion of a field plate electrode as a circuit element is formed of a resistive thin film.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a plan view for explaining a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA' in FIG. This example relates to an NPN transistor formed within a single crystal silicon island 101 embedded in a support substrate of polycrystalline silicon 113. Instead of a metal electrode such as aluminum, a silicon-chromium thin film resistor 111 is formed in an annular shape at the edge of the base diffusion layer 105 to serve as a field plate electrode. The emitter electrode 106 and base electrode 109 made of aluminum are in ohmic contact at a portion indicated by B in FIG.

Therefore, the resistance value of the resistor connected between the emitter and the base is the value of the right half and left half of the annular silicon-chromium thin film resistor 111 connected in parallel. The NPN transistor configured in this manner does not require any area for a resistor, and since there is no gap between the field plate electrodes, there is no reduction in breakdown voltage.

Next, a second embodiment of the present invention will be described. FIG. 3 is a plan view for explaining this embodiment, and FIG. 4 is a sectional view taken along line AA' in FIG. This embodiment shows an example of a lateral type PNP transistor. The field plate is used differently from the first embodiment by suppressing the depletion layer 215 extending from the collector diffusion layer 203 with an emitter-side field plate electrode formed of a silicon-chromium thin film resistor 211. 215 is prevented from contacting the emitter diffusion layer 207. In this embodiment, the silicon-chromium thin film resistor 211 is used as the field plate electrode and emitter resistor described above. That is, if the wiring is drawn out from the resistance electrode 214, a circuit in which a resistance is connected in series with the emitter is constructed. Portions C and D in FIG. 4 show ohmic contact surfaces between the silicon-chromium thin film resistor 211 and the emitter electrode 206, and between the silicon-chromium thin film resistor 211 and the resistance electrode 214, respectively.

[0009] Also in this embodiment, as in the first embodiment, no extra area is required for the resistor. The sheet resistance value of the silicon-chromium thin film resistor 211 is, for example, about 1.5 KΩ when the film thickness is about 10 nm, which is a value suitable for practical use.

0010

As explained above, in the present invention, by forming part or all of the field plate electrode of a transistor with a resistive thin film, the field plate electrode doubles as a resistor as a circuit element. This has the effect that the area of the semiconductor integrated circuit can be reduced.

Furthermore, since there are no opposing field plate electrodes, there is no suppression of the expansion of the depletion layer due to the gap between the pair of field plate electrodes, and there is no short circuit between the opposing field plate electrodes.

Specifically, for example, when comparing the first embodiment of the present invention with the conventional example, the area is reduced by about 15%. If the semiconductor integrated circuit device consists only of high voltage elements,
A maximum area reduction effect of 15% can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a plan view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining the first embodiment of the present invention, and is a sectional view taken along line AA' in FIG. 1.

FIG. 3 is a plan view for explaining a second embodiment of the present invention.

4 is a sectional view for explaining a second embodiment of the present invention, and is a sectional view taken along line AA' in FIG. 3. FIG.

FIG. 5 is a plan view for explaining a conventional technique.

FIG. 6 is a cross-sectional view for explaining a conventional technique, and is a cross-sectional view taken along line AA' in FIG.

FIG. 7 is a graph for explaining a conventional technique, and is a graph showing breakdown voltage characteristics of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

101, 201, 301a, 301b Single crystal silicon island 102, 202, 302 Collector electrode 103,
203, 303 Collector diffusion layer 104, 204
,304 Collector contact 105,205,
305 Base diffusion layer 106, 206 Emitter electrode 107, 207, 307 Emitter diffusion layer 108
, 208, 308 emitter contact 109,
209 Base electrode 110, 210, 310 Base contact 11
1,211,311 Silicon chromium thin film resistor 112,212,312 Silicon oxide film 113
,213,313 polycrystalline silicon 214
Resistance electrodes 215, 315 Depletion layer 306 Emitter field plate electrode 309
Base field plate electrodes 316a, 31
6b Wiring

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a plurality of circuit elements are formed on the main surface of a semiconductor substrate by a selective diffusion method, and electrodes of the circuit elements are connected by wiring, wherein the circuit element is a field plate electrode. 1. A semiconductor integrated circuit device, at least a portion of which is formed of a resistive thin film.