JPH1187334A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH1187334A JPH1187334A JP23922297A JP23922297A JPH1187334A JP H1187334 A JPH1187334 A JP H1187334A JP 23922297 A JP23922297 A JP 23922297A JP 23922297 A JP23922297 A JP 23922297A JP H1187334 A JPH1187334 A JP H1187334A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- semiconductor
- thermal oxide
- polycrystalline
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体装置におけ
る素子分離領域の製造方法に関するものである。The present invention relates to a method for manufacturing an element isolation region in a semiconductor device.
【0002】[0002]
【従来の技術】従来の素子分離領域の製造方法は、図2
のA〜Cの断面図に示す方法を用いていた。図にしたが
って説明する。Aのように、素子分離領域を形成する部
分のシリコン基板1の表面上に形成された酸化膜2を除
去し、残った前記酸化膜2をマスクとして前記シリコン
基板1の表面を任意の深さ3にエッチングする。次に、
Bのように、前記シリコン基板1の表面上全面に窒化膜
5を形成し、通常のフォトエッチング用レジストを形成
した後前記素子分離領域を形成する部分の前記レジスト
を除去し、残ったレジストをマスクとして前記窒化膜5
を除去する。最後に、Cのように、前記窒化膜5をマス
クとして1000℃以上の高温水蒸気酸素雰囲気中で素
子分離領域となる程度の厚さ8000〜10000Åに
熱酸化膜6を選択的に形成する。その後、前記窒化膜5
を除去し諸工程を付加して所望の半導体装置を完成させ
る。2. Description of the Related Art A conventional method for manufacturing an element isolation region is shown in FIG.
The method shown in the cross-sectional views of A to C was used. Description will be made with reference to the drawings. As shown in A, the oxide film 2 formed on the surface of the silicon substrate 1 at the portion where the element isolation region is to be formed is removed, and the surface of the silicon substrate 1 is removed to an arbitrary depth using the remaining oxide film 2 as a mask. Etch 3 next,
As shown in B, a nitride film 5 is formed on the entire surface of the silicon substrate 1, a normal photo-etching resist is formed, and then the resist in a portion where the element isolation region is to be formed is removed. The nitride film 5 as a mask
Is removed. Finally, as shown in C, using the nitride film 5 as a mask, a thermal oxide film 6 is selectively formed in a high-temperature steam oxygen atmosphere of 1000 ° C. or more at a thickness of 8000 to 10000 ° to be an element isolation region. Then, the nitride film 5
Is removed and various steps are added to complete a desired semiconductor device.
【0003】[0003]
【発明が解決しようとする課題】現在、半導体装置を製
造する際に加えられる熱工程は減少させる方向で検討が
進められている。これは、例えばバイポーラ・トランジ
スタを製造する場合コレクタとなる埋込層を形成する
が、後の工程で熱処理時間が長いとそれだけ埋込拡散層
のわき上がりが生じて埋込層厚の制御が難しくなるため
である。従来の技術では、通常の熱酸化工程で素子分離
用酸化膜を形成するためには長時間の熱処理が必要とな
る。また、短時間に厚い熱酸化膜を形成できる高圧酸化
炉があるが、新規に購入する場合、高額な設備投資が必
要となる。本発明の目的は、通常の熱酸化炉を使用して
厚い熱酸化膜を形成する際に必要な熱処理時間を低減す
ることができる半導体装置の製造方法を提供することに
ある。At present, studies are being made to reduce the number of thermal steps applied when manufacturing a semiconductor device. This is because, for example, when a bipolar transistor is manufactured, a buried layer serving as a collector is formed, but if the heat treatment time is long in a later step, the buried diffusion layer will rise to that extent, making it difficult to control the buried layer thickness. It is because it becomes. In the conventional technique, a long-time heat treatment is required to form an oxide film for element isolation in a normal thermal oxidation step. There is also a high-pressure oxidation furnace capable of forming a thick thermal oxide film in a short time, but when purchasing a new one, expensive equipment investment is required. An object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce a heat treatment time required for forming a thick thermal oxide film using a normal thermal oxidation furnace.
【0004】[0004]
【課題を解決するための手段】本発明は上記の目的を達
成するため、半導体表面の素子分離領域をエッチング
し、半導体表面上に単結晶と比較すると酸化速度が非常
に大きい多結晶半導体を形成し、選択的に熱酸化膜を形
成するようにしたものである。According to the present invention, in order to achieve the above object, an element isolation region on a semiconductor surface is etched to form a polycrystalline semiconductor having a much higher oxidation rate than a single crystal on a semiconductor surface. Then, a thermal oxide film is selectively formed.
【0005】作用について説明する。The operation will be described.
【0006】多結晶半導体は、単結晶のそれと比較する
と酸化速度が非常に大きいという性質がある。また、低
不純物濃度(1E15cm−3程度)の多結晶半導体は
絶縁材料に近いくらいの高抵抗性を示す。これらの性質
を利用すると、単結晶半導体上に通常の熱酸化工程で成
長させる酸化膜よりもはるかに厚い熱酸化膜を形成する
ことができる。言い換えれば、同じ厚さの熱酸化膜を形
成しようとした場合、より短時間の熱処理ですむことに
なる。また、多結晶半導体自体も低不純物濃度の場合絶
縁材料となるため、素子分離領域を形成するためには極
めて有効な手段となる。[0006] Polycrystalline semiconductors have the property that their oxidation rates are much higher than those of single crystals. In addition, a polycrystalline semiconductor having a low impurity concentration (about 1E15 cm −3) exhibits high resistance close to that of an insulating material. By utilizing these properties, it is possible to form a thermal oxide film much thicker than an oxide film grown on a single crystal semiconductor by a normal thermal oxidation process. In other words, if an attempt is made to form a thermal oxide film having the same thickness, a shorter heat treatment is required. Further, since the polycrystalline semiconductor itself becomes an insulating material when the impurity concentration is low, it is an extremely effective means for forming an element isolation region.
【0007】[0007]
【発明の実施の形態】以下、本発明の実施例を図1によ
り説明する。図1は本発明を説明するための断面図であ
る。図1Aのように、素子分離領域を形成する部分のシ
リコン基板1の表面上に形成された酸化膜2を除去し、
残った前記酸化膜2をマスクとして前記シリコン基板1
の表面を任意の深さ3にエッチングする。次に、図1B
のように、前記シリコン基板1の表面上全面に多結晶シ
リコン4を形成し、前記多結晶シリコン4上全面に窒化
膜5を形成し、通常のフォトエッチング用レジストを形
成した後前記素子分離領域を形成する部分の前記レジス
トを除去し、残ったレジストをマスクとして前記窒化膜
5を除去する。最後に、図1Cのように、前記窒化膜5
をマスクとして1000℃以上の高温水蒸気酸素雰囲気
中で素子分離領域となる程度の厚さに熱酸化膜6を選択
的に形成する。この熱酸化膜6は前記多結晶シリコン4
上に形成されることになる。また、通常の熱酸化装置で
形成するものである。その後、前記窒化膜5および素子
分離領域以外の前記多結晶シリコン4を除去し、諸工程
を付加して所望の半導体装置を完成させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a sectional view for explaining the present invention. As shown in FIG. 1A, the oxide film 2 formed on the surface of the silicon substrate 1 in the portion where the element isolation region is formed is removed,
Using the remaining oxide film 2 as a mask, the silicon substrate 1
Is etched to an arbitrary depth 3. Next, FIG. 1B
A polycrystalline silicon 4 is formed on the entire surface of the silicon substrate 1, a nitride film 5 is formed on the entire surface of the polycrystalline silicon 4, and a normal photo-etching resist is formed. Is removed, and the nitride film 5 is removed using the remaining resist as a mask. Finally, as shown in FIG.
Is used as a mask to selectively form a thermal oxide film 6 in a high-temperature steam oxygen atmosphere at a temperature of 1000 ° C. or more so as to have an element isolation region. This thermal oxide film 6 is
Will be formed on top. Further, it is formed by a normal thermal oxidation device. Thereafter, the polycrystalline silicon 4 other than the nitride film 5 and the element isolation region is removed, and various steps are added to complete a desired semiconductor device.
【0008】以上の工程は半導体のP,N極性にかかわ
らず実施できることは言うまでもない。また、本実施例
は通常の熱酸化装置を使用した場合について説明した
が、高圧酸化装置を使用した場合についてはさらに効果
が高い。すなわち、より短時間の熱処理で同じ厚さの熱
酸化膜を形成することができる。It goes without saying that the above steps can be performed regardless of the P and N polarities of the semiconductor. Further, in the present embodiment, the case where a normal thermal oxidizing apparatus is used has been described. However, the case where a high-pressure oxidizing apparatus is used is more effective. That is, a thermal oxide film having the same thickness can be formed by heat treatment in a shorter time.
【0009】[0009]
【発明の効果】多結晶半導体の酸化速度が非常に大き
い、また、低不純物濃度(1E15cm−3程度)の多
結晶半導体の高抵抗性という性質を利用すると、単結晶
半導体上に通常の熱酸化工程で成長させる酸化膜よりも
はるかに厚い熱酸化膜を形成することができる。言い換
えれば、同じ厚さの熱酸化膜を形成しようとした場合、
より短時間の熱処理ですむことになる。また、多結晶半
導体自体も低不純物濃度の場合絶縁材料となるため、素
子分離領域を形成するためには極めて有効な手段とな
る。その結果、この手法を用いることにより、高圧酸化
装置を用いずに従来の酸化炉でより短時間で、より厚い
素子分離領域用の熱酸化膜を形成することができる。The oxidation rate of a polycrystalline semiconductor is very high, and the high-resistance property of a polycrystalline semiconductor having a low impurity concentration (about 1E15 cm −3) is utilized to form a normal thermal oxidation on a single crystal semiconductor. A thermal oxide film much thicker than an oxide film grown in the process can be formed. In other words, when trying to form a thermal oxide film of the same thickness,
Shorter heat treatment is required. Further, since the polycrystalline semiconductor itself becomes an insulating material when the impurity concentration is low, it is an extremely effective means for forming an element isolation region. As a result, by using this technique, a thicker thermal oxide film for an element isolation region can be formed in a shorter time in a conventional oxidation furnace without using a high-pressure oxidation device.
【図1】本発明の一実施例の製造工程を示す断面図。FIG. 1 is a sectional view showing a manufacturing process according to one embodiment of the present invention.
【図2】従来の製造工程を示す断面図。FIG. 2 is a sectional view showing a conventional manufacturing process.
1:シリコン基板,2:酸化膜,3:任意の深さ,4:
多結晶シリコン,5:窒化膜,6:熱酸化膜1: silicon substrate, 2: oxide film, 3: arbitrary depth, 4:
Polycrystalline silicon, 5: nitride film, 6: thermal oxide film
Claims (1)
工程と、前記半導体表面上全面に多結晶半導体を形成
し、前記多結晶半導体上全面に窒化膜を形成する工程
と、前記半導体表面を前記エッチングした領域の前記窒
化膜を除去し、前記エッチング領域内の前記多結晶半導
体の熱酸化を行う工程とを有したことを特徴とする半導
体装置の製造方法。In a manufacturing process of a seed semiconductor device, a step of etching a predetermined position of a semiconductor surface to a predetermined depth, a step of forming a polycrystalline semiconductor on the entire surface of the semiconductor surface, and a step of forming a polycrystalline semiconductor on the entire surface of the polycrystalline semiconductor A semiconductor device, comprising: forming a nitride film; and removing the nitride film in a region where the semiconductor surface is etched, and thermally oxidizing the polycrystalline semiconductor in the etched region. Manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23922297A JPH1187334A (en) | 1997-09-04 | 1997-09-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23922297A JPH1187334A (en) | 1997-09-04 | 1997-09-04 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH1187334A true JPH1187334A (en) | 1999-03-30 |
Family
ID=17041573
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23922297A Pending JPH1187334A (en) | 1997-09-04 | 1997-09-04 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH1187334A (en) |
-
1997
- 1997-09-04 JP JP23922297A patent/JPH1187334A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH05109737A (en) | Manufacture of thin film transistor | |
JP2004128314A (en) | Method for manufacturing semiconductor device | |
JP3077760B2 (en) | Solid phase diffusion method | |
JPS6021558A (en) | Bi-polar type semiconductor integrated circuit device | |
JPH1187334A (en) | Manufacture of semiconductor device | |
JPS5812732B2 (en) | Manufacturing method for semiconductor devices | |
JPS5852843A (en) | Manufacture of semiconductor integrated circuit device | |
JPH04154162A (en) | Manufacture of mos-type semiconductor device | |
JPS612317A (en) | Manufacture of semiconductor device | |
JPS62104078A (en) | Manufacture of semiconductor integrated circuit device | |
JP2722829B2 (en) | Method for manufacturing semiconductor device | |
JPH01289165A (en) | Manufacture of semiconductor device | |
JPS6068656A (en) | Manufacture of semiconductor device | |
JPS63237568A (en) | Manufacture of semiconductor device | |
JPH0475349A (en) | Manufacture of semiconductor device | |
JPH04208570A (en) | Manufacture of semiconductor device | |
JPH053172A (en) | Semiconductor device and manufacture thereof | |
JPH0334322A (en) | Manufacture of semiconductor device | |
JPS6281765A (en) | Manufacture of silicon carbide device on silicon substrate | |
JP2000299374A (en) | Shallow trench etching method for element isolating silicon | |
JPS61147550A (en) | Manufacture of semiconductor device | |
JPS6080275A (en) | Manufacture of semiconductor device | |
JPH09266170A (en) | Manufacture of semiconductor device | |
JPS62101070A (en) | Manufacture of semiconductor device | |
JPH11233615A (en) | Manufacture of semiconductor device |