JPS612317A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS612317A JPS612317A JP59121762A JP12176284A JPS612317A JP S612317 A JPS612317 A JP S612317A JP 59121762 A JP59121762 A JP 59121762A JP 12176284 A JP12176284 A JP 12176284A JP S612317 A JPS612317 A JP S612317A
- Authority
- JP
- Japan
- Prior art keywords
- film
- furnace
- temperature
- atmosphere
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000012298 atmosphere Substances 0.000 claims abstract description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000007789 gas Substances 0.000 abstract description 12
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 230000008646 thermal stress Effects 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 238000010926 purge Methods 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000012495 reaction gas Substances 0.000 abstract description 2
- 238000004299 exfoliation Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000001603 reducing effect Effects 0.000 abstract 1
- 230000001629 suppression Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 9
- 150000002431 hydrogen Chemical class 0.000 description 6
- 238000005498 polishing Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 241001663154 Electron Species 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は主面上に5in2等の絶縁膜を有する半導体基
板を水素雰囲気中で加熱処理する工程を有する半導体装
置の製造方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an improvement in a method for manufacturing a semiconductor device, which includes a step of heat-treating a semiconductor substrate having an insulating film of 5 in 2 or the like on its main surface in a hydrogen atmosphere.
シリコンで代表される半導体基板上に回路素子を形成し
てなる半導体装置では、その製造プロセスの一部と1−
て水素(H2)ガス雰囲気中でシリコン基板を熱処理す
る工程がある。例えば、シリコン基板の主面に8102
等の絶縁膜をパターン形成した上で基板の露出された面
のみに選択的に単結晶シリコンを気相成長させる所謂選
択シリコンエピタキシャル成長法もその一つであり、H
2ガスはもとより他の反応ガス雰囲気下でシリコン基板
を約1100°C程度に加熱処理している、ところで、
このような選択エピタキシャル法の応用の一つとして、
I E DM (InternationalElec
tron Devices Meeting ) T
echnicalDigest 第241頁にはLS
Iの素子間分離技術に用いた例が示される。即ち、第1
図のようにシリコン基板1の主面に厚さ1〜2μmで形
成した5in2膜2をパターンエツチングすると共に、
露呈されたシリコン基板1の主面に反応ガスとしてS
i H2C4HC13Ht系を用いてこれを熱処埋する
ことにより単結晶シリコン層3なエピタキシャル成長さ
セ、これにより前記5102膜2を素子間分離領域とし
、単結晶シリコン層3を素子領域とし、所甜バーズビー
クの発生を抑えて素子の高集積化を図るようにしたもの
である。In semiconductor devices in which circuit elements are formed on a semiconductor substrate, typically silicon, there are some steps in the manufacturing process.
There is a step of heat-treating the silicon substrate in a hydrogen (H2) gas atmosphere. For example, 8102 on the main surface of a silicon substrate.
One such method is the so-called selective silicon epitaxial growth method, in which single-crystal silicon is selectively grown in vapor phase only on the exposed surface of the substrate after patterning an insulating film such as H
By the way, the silicon substrate is heat-treated to about 1100°C in an atmosphere of not only 2 gases but also other reactive gases.
One of the applications of such selective epitaxial method is
I E DM (International Elec
tron Devices Meeting ) T
LS on page 241 of mechanicalDigest
An example will be shown in which this method is used for isolation technology between elements. That is, the first
As shown in the figure, a 5in2 film 2 formed with a thickness of 1 to 2 μm on the main surface of a silicon substrate 1 is pattern-etched, and
S as a reactive gas is applied to the exposed main surface of the silicon substrate 1.
i By heat-treating this using H2C4HC13Ht system, a single crystal silicon layer 3 is epitaxially grown, whereby the 5102 film 2 is used as an element isolation region, the single crystal silicon layer 3 is used as an element region, and a bird's beak is formed. This is intended to suppress the occurrence of , and to achieve higher integration of the element.
しかしながら、このような選択エビクキシャル技術につ
いて本発明者が検討な行なったところ、処理の初期段階
においてSin、膜2に剥れが生じこれが半導体装置の
信頼性に悪影響を及ぼすことが明らかとされた。この剥
れは同図に示すように、5102膜2の端部から進行し
て空隙4が形成されるようになるもので、実験によれば
I−12雰囲気中で加熱しただけで発生している。即ち
、前述のエピタキシャル成長法においては、5iH2C
112゜HCl ガスを炉内に通流する前に、つまり
エピタキシャル成長屍始前にH2ガスのみを炉内に流す
工程がある。これは炉内の雰囲気を完全にH2で置換す
る必要があることと、H2によってシリコン表面を軽く
ガスエンチングして清浄なシリコン面を出す目的で行な
われるものであり、このH2中での熱工程でSiO2膜
2忙剥れが生じる。これらのことから、本発明者の推測
によれば、この剥れはH2により5in2が還元作用を
受け、これにストレスや熱膨張係数の差等の効果が加わ
ることにより発生するものと考えられる。However, when the present inventor investigated such a selective eviction technique, it was found that peeling of the Sin film 2 occurs in the initial stage of processing, which adversely affects the reliability of the semiconductor device. As shown in the figure, this peeling progresses from the edge of the 5102 film 2 to form voids 4, and according to experiments, it occurs simply by heating in an I-12 atmosphere. There is. That is, in the epitaxial growth method described above, 5iH2C
Before flowing 112° HCl gas into the furnace, that is, before the epitaxial growth begins, there is a step of flowing only H2 gas into the furnace. This is done because it is necessary to completely replace the atmosphere in the furnace with H2, and to lightly gas-etch the silicon surface with H2 to expose a clean silicon surface. The SiO2 film 2 peels off. Based on these facts, the present inventor conjectures that this peeling is caused by the reduction action of 5in2 by H2 and the addition of effects such as stress and a difference in coefficient of thermal expansion.
このため、前記文献においては第2図のようにSin2
M2の側壁をシリコンナイトライド(SisN4)膜5
で被い、H2の攻撃から5IO2を保護する方法を提案
している。しかしながら、この対策によっても剥れを確
実に防止することは困難である。Therefore, in the above literature, as shown in Fig. 2, Sin2
A silicon nitride (SisN4) film 5 is formed on the side wall of M2.
proposed a method to protect 5IO2 from H2 attacks. However, even with this measure, it is difficult to reliably prevent peeling.
〔発明の目的1
本発明の目的は主面上に5102膜のような絶縁膜を有
する半導体基板なH2雰囲気中で熱処理しても絶縁膜に
剥れが生じることがなく、したがって信頼性の高い半導
体装置を容易に製造することのできる製造方法を提供す
ることにある。[Objective of the Invention 1 The object of the present invention is to provide a semiconductor substrate having an insulating film such as 5102 film on its main surface, which will not peel off even when heat-treated in an H2 atmosphere, and therefore have high reliability. An object of the present invention is to provide a manufacturing method that can easily manufacture a semiconductor device.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示されろ発明のうち代表的なものの概要
を簡単に説明すれば、下記Q)とおりであ杭
すなわち、主面にSiO2膜等の絶縁膜を有する半導体
基板なH2雰囲気吊で熱処理するに際し、その温度を]
050°C以下に規制することfより、特に絶縁膜にお
ける熱ストレスの低減およびH7還元作用の抑制を図っ
て絶縁膜における剥れを防止し、かつこれにより信頼性
の高い半導体装置を製造することができるものである。A brief summary of the typical inventions disclosed in this application is as follows Q). In other words, when a semiconductor substrate having an insulating film such as a SiO2 film on its main surface is heat-treated in an H2 atmosphere, , that temperature]
By regulating the temperature to 050°C or less, we aim to reduce the thermal stress in the insulating film in particular and suppress the H7 reduction action to prevent peeling in the insulating film, and thereby manufacture highly reliable semiconductor devices. It is something that can be done.
これを詳しく説明すれば次のとおりである。This will be explained in detail as follows.
本発明者が種々の適用を試みシリコン基板上におけるS
iO□膜の剥れについて検討したところ、剥れはH2雰
囲気におけろ熱処理温度と強い相関のあることが判明し
た。即ち、バターニングした5I02膜を有するシリコ
ン基板なH2雰囲気中において種々の温度で熱処理し、
その剥れ量lと温度T′Oの関係を求めたところ、第3
図の相関図が得られた。これから、5in2膜の剥れは
10700膜以上で発生し、かつ温度が高いほどその程
度が大きいことが判り、逆に見れば1070℃より下、
温度ばらつき等を考慮し、でも1050°C以下にすれ
ば剥れの発生が防止できることが判る。したがって、H
2雰囲気で熱処理を行なうプロセスにおいて、その熱処
理温度を1050°C以下にすればシリコン基板におけ
ろ5L02膜の剥れを防止して信頼性の向上を図ること
が判る。The present inventor has tried various applications of S on silicon substrates.
When examining the peeling of the iO□ film, it was found that peeling has a strong correlation with the heat treatment temperature in an H2 atmosphere. That is, a silicon substrate having a buttered 5I02 film was heat-treated at various temperatures in an H2 atmosphere, and
When we calculated the relationship between the amount of peeling l and the temperature T'O, we found that
A correlation diagram of the figure was obtained. From this, it can be seen that peeling of the 5in2 film occurs above 10,700°C, and the higher the temperature, the greater the degree of peeling.
It can be seen that peeling can be prevented by setting the temperature to 1050°C or less, taking into account temperature variations. Therefore, H
It can be seen that in a process in which heat treatment is performed in two atmospheres, if the heat treatment temperature is set to 1050° C. or lower, peeling of the 5L02 film on a silicon substrate can be prevented and reliability can be improved.
第4図は本発明をNチャネルMO8LSIに適用1−だ
場合の、特に素子間分離技術に適用した実施例である。FIG. 4 shows an example in which the present invention is applied to an N-channel MO8LSI, in particular to an isolation technique between elements.
まず、第4図(イ)のようにP型のシリコン基板11を
熱酸化して5102膜12を形成し、これを図外のフォ
トレジストをマスクにして同図03)のようにパターニ
ングする。この残された5102膜12aは素子分離領
域として構成される。First, as shown in FIG. 4(A), a P-type silicon substrate 11 is thermally oxidized to form a 5102 film 12, and this is patterned as shown in FIG. 3) using a photoresist (not shown) as a mask. This remaining 5102 film 12a is configured as an element isolation region.
次K、フォトレジストを除去した後、同図(clのよう
にシリコン基板11の露出している部分のみに選択的K
P型の単結晶シリコンN13をエビタキシャル成長させ
、前記5102膜12aの上に張り出すように充分に厚
く形成するーこのエピタキシャル成長に際しては、S
r H2C13,、−HCiJ −N2系を反応ガスと
して用いるが、このときのプロセスは第5図のように行
なう、ます、炉内にN2ガスか導入して炉内をN2雰囲
気としくN2パージ)、続いて雰囲気をN2に切換えN
2パージを行なった後N2雰囲気のまま炉内を所定の温
度まで上昇させろ。この温度としては前述の理由により
】050°C以下に設定する。炉内温度が所定温度に達
し数分経過した後に5iH2Cノ、 、HC7ガスを炉
内に通流する。これによりエピタキシャル成長が開始さ
れる。所定の時間だけエピタキシャル成長を行なった後
S 1H2C12、HC,/! の供給を停止し、炉
内を再びN2で置換して数分後炉内の温度を降下させ始
め室温まで降下させて処理を完了する。Next, after removing the photoresist, selective K is applied only to the exposed part of the silicon substrate 11 as shown in the same figure (cl).
P-type single crystal silicon N13 is epitaxially grown to be sufficiently thick so as to overhang the 5102 film 12a. During this epitaxial growth, S
r H2C13, -HCiJ -N2 system is used as the reaction gas, and the process at this time is carried out as shown in Figure 5. First, N2 gas is introduced into the furnace to create an N2 atmosphere inside the furnace and N2 purge) , then switch the atmosphere to N2
After performing two purges, raise the temperature inside the furnace to a predetermined temperature while maintaining the N2 atmosphere. This temperature is set to 050°C or less for the reasons mentioned above. After several minutes have elapsed since the temperature in the furnace reached a predetermined temperature, 5iH2C, HC7 gases were passed into the furnace. This starts epitaxial growth. After performing epitaxial growth for a predetermined period of time, S 1H2C12,HC,/! The supply of gas is stopped, the inside of the furnace is replaced with N2, and after a few minutes, the temperature inside the furnace begins to drop to room temperature, and the process is completed.
次いで、同図G)1のように通常のウェーハ鏡面壮士げ
に用いられている方法でシリコン基板110表面を研磨
し、S10.膜12aより上に出た部分の単結晶シリコ
ン層13をその上面が5in2膜12aの上面と一致す
るまで研磨する。これにより、素子領域13aと素子間
分離領域12aとからなる平坦性の高いウェーハが形成
できる。こうして得られた素子領域(単結晶シリコン層
)]3aに通常プロセスに従って第6図に示すようにゲ
ート絶縁膜14、ゲート電極15、ソース・ドレイン領
域16a、16bからなるNチャネル型のMOSトラン
ジスタを形成する。Next, the surface of the silicon substrate 110 is polished by a method commonly used for polishing wafers, as shown in G) 1 of the same figure, and S10. The portion of the single crystal silicon layer 13 exposed above the film 12a is polished until its upper surface coincides with the upper surface of the 5in2 film 12a. As a result, a highly flat wafer consisting of the element region 13a and the inter-element isolation region 12a can be formed. An N-channel MOS transistor consisting of a gate insulating film 14, a gate electrode 15, and source/drain regions 16a and 16b is formed in the thus obtained device region (single crystal silicon layer) 3a according to a normal process as shown in FIG. Form.
ここで、第7図囚のように素子間分離領域と[−でのS
iO,、膜12a土にCVD法等によってS i 3N
4膜17を耐磨耗性膜として形成1−ておいてもよい。Here, as shown in Figure 7, the element isolation region and the S
iO,, S i 3N is applied to the soil of the film 12a by CVD method etc.
The fourth film 17 may be formed as a wear-resistant film.
このSi、N+l漠17を形成しておくことにより、同
図山)に示す単結晶シリコン層13の研磨時に単結晶シ
リコン層13とSi、N4膜17どの研磨速度比が50
:lであることから精度良く平坦イヒすることができる
。なお、単結晶シリコン層13と5in2膜12aとの
研磨速度比は15:1である。By forming this Si, N+l film 17, the polishing rate ratio between the single crystal silicon layer 13 and the Si, N4 film 17 is 50 when polishing the single crystal silicon layer 13 shown in the same figure).
:L, it is possible to achieve a flat surface with high accuracy. Note that the polishing rate ratio between the single crystal silicon layer 13 and the 5in2 film 12a is 15:1.
研磨後は、同図(C)のように素子領域としての単結晶
7927層13aの表面を酸化して保護用の5i02膜
18を形成し、しかる土でSi3N4膜17をエツチン
グ除去しく同図の))、かつその後に5i02膜18を
除去することにより同図旧)のように平坦7.cウェー
ハを得ろことができる。After polishing, as shown in the figure (C), the surface of the single crystal 7927 layer 13a serving as the element region is oxidized to form a protective 5i02 film 18, and the Si3N4 film 17 is etched away using soil. )), and then by removing the 5i02 film 18, a flat surface 7. C wafers can be obtained.
以上の実施例によれば、H,ガス雰囲気におけろ熱処理
、本例ではエピタキシャル成長を1050℃以下の温度
で処理して℃糞1ので、シリコン基板11の表面に設け
ているS s Oを膜12aK生じる還元作用や熱スト
レスは低減され、これにより5i02膜12aの剥れは
防止でき、これにより素子間分離領域ないし半導体装置
全体の信頼性を高いものにすることができる。According to the embodiments described above, the epitaxial growth is performed at a temperature of 1050° C. or less in an H gas atmosphere, and in this example, the epitaxial growth is performed at a temperature of 1050° C., so that the S s O provided on the surface of the silicon substrate 11 is formed into a film. The reduction action and thermal stress caused by 12aK are reduced, thereby preventing the 5i02 film 12a from peeling off, thereby increasing the reliability of the element isolation region or the entire semiconductor device.
(1)表面KSiO2膜を有するシリコン基板をエピタ
キシャル成長のようにN2ガス雰囲気下で熱処理するに
際し、その温度を1050℃以下に設定[7ているので
、Sin、膜における還元作用と熱ストレスの発生を抑
止し、これにより5I02膜の剥り、す防止すa)こと
ができるという効果を奏する。(1) When heat-treating a silicon substrate with a surface KSiO2 film in an N2 gas atmosphere, such as during epitaxial growth, the temperature is set to 1050°C or lower [7], so that the reduction effect and thermal stress in the Si film can be reduced. This has the effect of preventing the 5I02 film from peeling off.
(2)素子分離領域としての8102膜を設けたシリコ
ン基板に対し、素子領域としての単結晶シリコン層をエ
ピタキシャル成長させる際にその温度を1050℃以下
に設定しているので、素子分離領域としての信頼性を向
上させ、かつその後における研摩てよ−ても破損される
ことがないので、高い信頼性の半導体装置を得ることが
できる。(2) When the single-crystal silicon layer as the element region is epitaxially grown on the silicon substrate provided with the 8102 film as the element isolation region, the temperature is set at 1050°C or less, so it is reliable as the element isolation region. It is possible to obtain a highly reliable semiconductor device because it has improved properties and is not damaged even during subsequent polishing.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、ンリコン以
外の半導体装おける熱処理においても、また5in2膜
以外の絶縁膜を有する場合にも同様に実施することがで
きる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the same heat treatment can be applied to semiconductor devices other than non-conductive semiconductor devices, and also when the semiconductor device has an insulating film other than a 5in2 film.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である単結晶シリコンのエ
ピタキシャル成長技術icJ用し、た場合について説明
したが、それに限定されるものではなく、N2雰囲気で
熱処理するプロセスであればベーバエ、チング等の他の
処理においても同様に適用することができる。In the above explanation, the invention made by the present inventor is mainly applied to the ICJ epitaxial growth technology of single crystal silicon, which is the field of application for which the invention is based, but the invention is not limited to this, and the invention is not limited to this. As long as the process involves heat treatment, it can be similarly applied to other treatments such as heating and scratching.
第1図は従来の不具合を説明する断面図、第2図は従来
対策の一例を示す断面図、第3図は本発明の詳細な説明
する特性図、第4図w〜の)は本発明を適用した実施例
プロセスの工程断面図、
第5図は温度の制御グラフ、
第6図はNチャネルMO8)ランジスタの断面図、
第7図囚)〜(Elは他の例の工程断面図である。
11=−半導体基板、] 2. 12 a−8i02膜
(絶縁膜)、13.13a・・・単結晶シリコン層(素
子領域)、】4・・・ゲート絶縁膜、15・・・ゲート
電極、1.6a、16b・・ンース・ドレイン領域、]
7・・Si3N4膜(耐磨耗性膜)、J8・・・5i0
21i!0第 2 図
憑尽(′C〕
第 4 図
(A)
第 5 図
第°5図Fig. 1 is a cross-sectional view explaining the conventional problem, Fig. 2 is a cross-sectional view showing an example of the conventional countermeasure, Fig. 3 is a characteristic diagram explaining the present invention in detail, and Fig. 4 w~) are the present invention. Figure 5 is a temperature control graph, Figure 6 is a cross-sectional view of an N-channel MO8) transistor, Figure 7 is a process cross-sectional diagram of an example process in which 11=-semiconductor substrate, ] 2. 12 a-8i02 film (insulating film), 13. 13a... single crystal silicon layer (device region), ] 4... gate insulating film, 15... gate Electrodes, 1.6a, 16b... drain region, ]
7...Si3N4 film (wear-resistant film), J8...5i0
21i! 0 2nd Illustration ('C) Figure 4 (A) Figure 5 °5
Claims (1)
を高温の水素雰囲気中で熱処理する工程を含む半導体装
置の製造方法において、前記熱処理温度を1050℃以
下にしたことを特徴とする半導体装置の製造方法。 2、シリコン基板の主面上に二酸化シリコン膜を選択形
成し、この二酸化シリコン膜以外の前記シリコン基板の
主面に単結晶シリコンをエピタキシャル成長させてなり
、このエピタキシャル成長時の温度を1050℃以下に
してなる特許請求の範囲第1項記載の半導体装置の製造
方法。[Claims] 1. A method for manufacturing a semiconductor device including a step of heat-treating a semiconductor substrate having an insulating film pattern on its main surface in a high-temperature hydrogen atmosphere, wherein the heat treatment temperature is set to 1050° C. or less. A method for manufacturing a semiconductor device, characterized by: 2. A silicon dioxide film is selectively formed on the main surface of a silicon substrate, and single crystal silicon is epitaxially grown on the main surface of the silicon substrate other than this silicon dioxide film, and the temperature during this epitaxial growth is 1050°C or less. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59121762A JPS612317A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59121762A JPS612317A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS612317A true JPS612317A (en) | 1986-01-08 |
Family
ID=14819252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59121762A Pending JPS612317A (en) | 1984-06-15 | 1984-06-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS612317A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344717A (en) * | 1986-03-31 | 1988-02-25 | Canon Inc | Manufacture of crystal and crystalline articles obtained by said manufacture |
JPH01132118A (en) * | 1987-08-24 | 1989-05-24 | Canon Inc | Preparation of semiconductor crystal and semiconductor crystal product obtained thereby |
JPH01157517A (en) * | 1987-08-24 | 1989-06-20 | Canon Inc | Formation of crystal |
US6043490A (en) * | 1997-01-27 | 2000-03-28 | Hitachi, Ltd. | Vibration cancellation system for a charged particle beam apparatus |
JP2004152920A (en) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Method of manufacturing semiconductor device and method of managing semiconductor manufacturing process |
-
1984
- 1984-06-15 JP JP59121762A patent/JPS612317A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6344717A (en) * | 1986-03-31 | 1988-02-25 | Canon Inc | Manufacture of crystal and crystalline articles obtained by said manufacture |
JPH01132118A (en) * | 1987-08-24 | 1989-05-24 | Canon Inc | Preparation of semiconductor crystal and semiconductor crystal product obtained thereby |
JPH01157517A (en) * | 1987-08-24 | 1989-06-20 | Canon Inc | Formation of crystal |
US6043490A (en) * | 1997-01-27 | 2000-03-28 | Hitachi, Ltd. | Vibration cancellation system for a charged particle beam apparatus |
JP2004152920A (en) * | 2002-10-30 | 2004-05-27 | Fujitsu Ltd | Method of manufacturing semiconductor device and method of managing semiconductor manufacturing process |
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